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[topgen] Improve support for multiple address spaces
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With this change, topgen supports MMIO regions in multiple address
spaces. It requires to associate each memory to an address space.
Further, topgen generates definies for peripheral interface for
all address spaces. For Darjeeling, that means the SOC facing
interfaces, e.g., the SOC port of the mailbox, get their base
addresss definitions and the size of the address window.

Signed-off-by: Robert Schilling <[email protected]>
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@Razer6
Razer6 committed May 4, 2024
1 parent f4962c8 commit c502130
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Showing 18 changed files with 1,008 additions and 83 deletions.
3 changes: 3 additions & 0 deletions hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson
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Expand Up @@ -3763,6 +3763,7 @@
exec: True
byte_write: True
size: 0x40000000
addr_space: hart
}
}
clock_connections:
Expand Down Expand Up @@ -4092,6 +4093,7 @@
exec: True
byte_write: True
size: 0x1000
addr_space: hart
}
}
clock_connections:
Expand Down Expand Up @@ -6104,6 +6106,7 @@
exec: True
byte_write: True
size: 0x10000
addr_space: hart
}
}
clock_connections:
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5 changes: 4 additions & 1 deletion hw/top_darjeeling/data/top_darjeeling.hjson
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Expand Up @@ -537,6 +537,7 @@
exec: "True",
byte_write: "True",
size: "0x40000000",
addr_space: "hart"
}
}
},
Expand All @@ -562,7 +563,8 @@
data_intg_passthru: "true",
exec: "True",
byte_write: "True",
size: "0x1000"
size: "0x1000",
addr_space: "hart"
}
}
},
Expand Down Expand Up @@ -716,6 +718,7 @@
exec: "True",
byte_write: "True",
size: "0x10000"
addr_space: "hart"
}
}
},
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120 changes: 120 additions & 0 deletions hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv
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Expand Up @@ -91,6 +91,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES = 32'h100;

/**
* Peripheral base address for dmi device on lc_ctrl in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR = 32'h20000;

/**
* Peripheral size in bytes for dmi device on lc_ctrl in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES = 32'h1000;

/**
* Peripheral base address for alert_handler in top darjeeling.
*/
Expand Down Expand Up @@ -241,6 +251,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES = 32'h1000;

/**
* Peripheral base address for dbg device on rv_dm in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_RV_DM_DBG_BASE_ADDR = 32'h0;

/**
* Peripheral size in bytes for dbg device on rv_dm in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES = 32'h200;

/**
* Peripheral base address for rv_plic in top darjeeling.
*/
Expand Down Expand Up @@ -431,6 +451,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_MBX0_CORE_SIZE_BYTES = 32'h80;

/**
* Peripheral base address for soc device on mbx0 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX0_SOC_BASE_ADDR = 32'h1465000;

/**
* Peripheral size in bytes for soc device on mbx0 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX0_SOC_SIZE_BYTES = 32'h20;

/**
* Peripheral base address for core device on mbx1 in top darjeeling.
*/
Expand All @@ -441,6 +471,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_MBX1_CORE_SIZE_BYTES = 32'h80;

/**
* Peripheral base address for soc device on mbx1 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX1_SOC_BASE_ADDR = 32'h1465100;

/**
* Peripheral size in bytes for soc device on mbx1 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX1_SOC_SIZE_BYTES = 32'h20;

/**
* Peripheral base address for core device on mbx2 in top darjeeling.
*/
Expand All @@ -451,6 +491,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_MBX2_CORE_SIZE_BYTES = 32'h80;

/**
* Peripheral base address for soc device on mbx2 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX2_SOC_BASE_ADDR = 32'h1465200;

/**
* Peripheral size in bytes for soc device on mbx2 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX2_SOC_SIZE_BYTES = 32'h20;

/**
* Peripheral base address for core device on mbx3 in top darjeeling.
*/
Expand All @@ -461,6 +511,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_MBX3_CORE_SIZE_BYTES = 32'h80;

/**
* Peripheral base address for soc device on mbx3 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX3_SOC_BASE_ADDR = 32'h1465300;

/**
* Peripheral size in bytes for soc device on mbx3 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX3_SOC_SIZE_BYTES = 32'h20;

/**
* Peripheral base address for core device on mbx4 in top darjeeling.
*/
Expand All @@ -471,6 +531,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_MBX4_CORE_SIZE_BYTES = 32'h80;

/**
* Peripheral base address for soc device on mbx4 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX4_SOC_BASE_ADDR = 32'h1465400;

/**
* Peripheral size in bytes for soc device on mbx4 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX4_SOC_SIZE_BYTES = 32'h20;

/**
* Peripheral base address for core device on mbx5 in top darjeeling.
*/
Expand All @@ -481,6 +551,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_MBX5_CORE_SIZE_BYTES = 32'h80;

/**
* Peripheral base address for soc device on mbx5 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX5_SOC_BASE_ADDR = 32'h1465500;

/**
* Peripheral size in bytes for soc device on mbx5 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX5_SOC_SIZE_BYTES = 32'h20;

/**
* Peripheral base address for core device on mbx6 in top darjeeling.
*/
Expand All @@ -491,6 +571,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_MBX6_CORE_SIZE_BYTES = 32'h80;

/**
* Peripheral base address for soc device on mbx6 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX6_SOC_BASE_ADDR = 32'h1465600;

/**
* Peripheral size in bytes for soc device on mbx6 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX6_SOC_SIZE_BYTES = 32'h20;

/**
* Peripheral base address for core device on mbx_jtag in top darjeeling.
*/
Expand All @@ -501,6 +591,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES = 32'h80;

/**
* Peripheral base address for soc device on mbx_jtag in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR = 32'h1000;

/**
* Peripheral size in bytes for soc device on mbx_jtag in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES = 32'h20;

/**
* Peripheral base address for core device on mbx_pcie0 in top darjeeling.
*/
Expand All @@ -511,6 +611,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES = 32'h80;

/**
* Peripheral base address for soc device on mbx_pcie0 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR = 32'h1460100;

/**
* Peripheral size in bytes for soc device on mbx_pcie0 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES = 32'h20;

/**
* Peripheral base address for core device on mbx_pcie1 in top darjeeling.
*/
Expand All @@ -521,6 +631,16 @@ package top_darjeeling_pkg;
*/
parameter int unsigned TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES = 32'h80;

/**
* Peripheral base address for soc device on mbx_pcie1 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR = 32'h1460200;

/**
* Peripheral size in bytes for soc device on mbx_pcie1 in top darjeeling.
*/
parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES = 32'h20;

/**
* Peripheral base address for cfg device on rv_core_ibex in top darjeeling.
*/
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