[RV_DM] rv_dm_jtag_dtm_hard_reset_vseq

This test verify that after performing the operation of hard reset the debug module still responds correctly. Signed-off-by: Basit Mehmood <[email protected]>
lowRISC · Jan 18, 2024 · bfb97b1 · bfb97b1
1 parent ffe3a9d
commit bfb97b1
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/hw/ip/rv_dm/dv/rv_dm_sim_cfg.hjson b/hw/ip/rv_dm/dv/rv_dm_sim_cfg.hjson
@@ -247,7 +247,7 @@
     }
     {
       name: rv_dm_jtag_dtm_hard_reset
-      uvm_test_seq: rrv_dm_jtag_dtm_hard_reset_vseq
+      uvm_test_seq: rv_dm_jtag_dtm_hard_reset_vseq
       reseed: 2
     }
   ]