[topgen] Improve support for multiple address spaces

Individually generate C and Rust collateral for all address spaces

Signed-off-by: Robert Schilling <[email protected]>

hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson

@@ -454,6 +454,7 @@
     {
       name: hart
       desc: The main address space, shared between the CPU and DM
+      default: true
     }
     {
       name: soc_mbx

hw/top_darjeeling/data/top_darjeeling.hjson

@@ -166,7 +166,7 @@
   // all peripherals, though not every peripheral will be accessible to every
   // host in that address space--Access privileges are separate from addresses.
   addr_spaces: [
-    { name: "hart", desc: "The main address space, shared between the CPU and DM"},
+    { name: "hart", desc: "The main address space, shared between the CPU and DM", default: true},
     { name: "soc_mbx", desc: "SoC address space for mailbox access"},
     { name: "soc_dbg", desc: "SoC address space for debug module interfaces"},
   ]

hw/top_darjeeling/data/xbar_second.hjson

@@ -0,0 +1,70 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{ name: "second",
+  type: "xbar",
+  clock_primary: "clk_main_i", // Main clock, used in sockets
+  other_clock_list: [ "clk_fixed_i", "clk_usb_i"] // Secondary clocks used by specific nodes
+  reset_primary: "rst_main_ni", // Main reset, used in sockets
+  other_reset_list: [ "rst_fixed_ni", "rst_usb_ni"] // Secondary resets used by specific nodes
+
+  // Rationale for pipeline and req/rsp_fifo_pass:
+  // For host interfaces that are used during production state (corei/cored),
+  // minimize the amount of host introduced latency.  This is accomplished
+  // by setting pipeline to false.
+  // For host interfaces that are only used for debug, relax the timing by
+  // inserting a register slice and not allowing passthrough (more access
+  // latency. This is accomplished by setting `req/rsp_fifo_pass` to false,
+  // and implicitly using the default of pipeline true.
+  //
+  // For device interfaces, especially configuration registers, latency is
+  // not generally a concern, thus use `req/rsp_fifo_pass` false and pipeline
+  // true.
+  // For device accesses to memories (ram / rom / flash), performance is a concern,
+  // so use pipeline false where permissible by timing. If not, find a combination
+  // that works.
+  nodes: [
+    { name:  "rv_core_ibex_second.corei",
+      type:  "host",
+      addr_space: "hart_second",
+      clock: "clk_main_i",
+      reset: "rst_main_ni",
+      pipeline: false
+    },
+    { name:  "rv_core_ibex_second.cored",
+      type:  "host",
+      addr_space: "hart_second",
+      clock: "clk_main_i",
+      reset: "rst_main_ni",
+      pipeline: false
+    },
+    { name:      "rv_core_ibex_second.cfg",
+      type:      "device",
+      clock:     "clk_main_i"
+      reset:     "rst_main_ni"
+      req_fifo_pass: false,
+      rsp_fifo_pass: false,
+    },
+    { name:      "sram_ctrl_second.regs",
+      type:      "device",
+      clock:     "clk_main_i",
+      reset:     "rst_main_ni",
+      req_fifo_pass: false,
+      rsp_fifo_pass: false,
+    },
+    { name:      "sram_ctrl_second.ram",
+      type:      "device",
+      clock:     "clk_main_i",
+      reset:     "rst_main_ni",
+      pipeline:  false
+    },
+  ],
+  connections: {
+    // TODO: remove rv_core_ibex_second.corei - sram_ctrl_second.ram connection
+    rv_core_ibex_second.corei:  ["sram_ctrl_second.ram"],
+    rv_core_ibex_second.cored:  [
+      "sram_ctrl_second.ram", "sram_ctrl_second.regs",
+      "rv_core_ibex_second.cfg"
+    ]
+  },
+}

hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_dbg_pkg.sv

@@ -0,0 +1,46 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \
+//                -o hw/top_darjeeling/ \
+//                --rnd_cnst_seed \
+//                1017106219537032642877583828875051302543807092889754935647094601236425074047
+
+package top_darjeeling_pkg;
+  /**
+   * Peripheral base address for dmi device on lc_ctrl in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR = 32'h20000;
+
+  /**
+   * Peripheral size in bytes for dmi device on lc_ctrl in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES = 32'h1000;
+
+  /**
+   * Peripheral base address for dbg device on rv_dm in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_RV_DM_DBG_BASE_ADDR = 32'h0;
+
+  /**
+   * Peripheral size in bytes for dbg device on rv_dm in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES = 32'h200;
+
+  /**
+   * Peripheral base address for soc device on mbx_jtag in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR = 32'h1000;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx_jtag in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES = 32'h20;
+
+
+
+endpackage

hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_mbx_pkg.sv

@@ -0,0 +1,106 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \
+//                -o hw/top_darjeeling/ \
+//                --rnd_cnst_seed \
+//                1017106219537032642877583828875051302543807092889754935647094601236425074047
+
+package top_darjeeling_pkg;
+  /**
+   * Peripheral base address for soc device on mbx0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX0_SOC_BASE_ADDR = 32'h1465000;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX0_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX1_SOC_BASE_ADDR = 32'h1465100;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX1_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx2 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX2_SOC_BASE_ADDR = 32'h1465200;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx2 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX2_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx3 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX3_SOC_BASE_ADDR = 32'h1465300;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx3 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX3_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx4 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX4_SOC_BASE_ADDR = 32'h1465400;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx4 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX4_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx5 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX5_SOC_BASE_ADDR = 32'h1465500;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx5 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX5_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx6 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX6_SOC_BASE_ADDR = 32'h1465600;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx6 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX6_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx_pcie0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR = 32'h1460100;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx_pcie0 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES = 32'h20;
+
+  /**
+   * Peripheral base address for soc device on mbx_pcie1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR = 32'h1460200;
+
+  /**
+   * Peripheral size in bytes for soc device on mbx_pcie1 in top darjeeling.
+   */
+  parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES = 32'h20;
+
+
+
+endpackage

hw/top_darjeeling/sw/autogen/chip/mod.rs

@@ -4,3 +4,7 @@
 
 pub mod top_darjeeling;
 pub mod top_darjeeling_memory;
+pub mod top_darjeeling_soc_mbx;
+pub mod top_darjeeling_soc_mbx_memory;
+pub mod top_darjeeling_soc_dbg;
+pub mod top_darjeeling_soc_dbg_memory;

hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg.rs

@@ -0,0 +1,71 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file was generated automatically.
+// Please do not modify content of this file directly.
+// File generated by using template: "toplevel.rs.tpl"
+// To regenerate this file follow OpenTitan topgen documentations.
+
+#![allow(dead_code)]
+
+//! This file contains enums and consts for use within the Rust codebase.
+//!
+//! These definitions are for information that depends on the top-specific chip
+//! configuration, which includes:
+//! - Device Memory Information (for Peripherals and Memory)
+//! - PLIC Interrupt ID Names and Source Mappings
+//! - Alert ID Names and Source Mappings
+//! - Pinmux Pin/Select Names
+//! - Power Manager Wakeups
+
+use core::convert::TryFrom;
+
+/// Peripheral base address for dmi device on lc_ctrl in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR: usize = 0x20000;
+
+/// Peripheral size for dmi device on lc_ctrl in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and
+/// `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`.
+pub const TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES: usize = 0x1000;
+/// Peripheral base address for dbg device on rv_dm in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_RV_DM_DBG_BASE_ADDR: usize = 0x0;
+
+/// Peripheral size for dbg device on rv_dm in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and
+/// `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`.
+pub const TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES: usize = 0x200;
+/// Peripheral base address for soc device on mbx_jtag in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR: usize = 0x1000;
+
+/// Peripheral size for soc device on mbx_jtag in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES: usize = 0x20;
+
+
+/// MMIO Region
+///
+/// MMIO region excludes any memory that is separate from the module
+/// configuration space, i.e. ROM, main SRAM, and flash are excluded but
+/// retention SRAM, spi_device memory, or usbdev memory are included.
+pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x1000;
+pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0x20000;

hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg_memory.rs

@@ -0,0 +1,62 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file was generated automatically.
+// Please do not modify content of this file directly.
+// File generated by using template: "toplevel_memory.rs.tpl"
+// To regenerate this file follow OpenTitan topgen documentations.
+
+#![allow(dead_code)]
+
+//! Rust Top-Specific Definitions.
+//!
+//! This file contains const definitions for use within Rust code.
+
+/// Peripheral base address for dmi device on lc_ctrl in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR: usize = 0x20000;
+
+/// Peripheral size for dmi device on lc_ctrl in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and
+/// `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`.
+pub const TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES: usize = 0x1000;
+/// Peripheral base address for dbg device on rv_dm in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_RV_DM_DBG_BASE_ADDR: usize = 0x0;
+
+/// Peripheral size for dbg device on rv_dm in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and
+/// `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`.
+pub const TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES: usize = 0x200;
+/// Peripheral base address for soc device on mbx_jtag in top darjeeling.
+///
+/// This should be used with #mmio_region_from_addr to access the memory-mapped
+/// registers associated with the peripheral (usually via a DIF).
+pub const TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR: usize = 0x1000;
+
+/// Peripheral size for soc device on mbx_jtag in top darjeeling.
+///
+/// This is the size (in bytes) of the peripheral's reserved memory area. All
+/// memory-mapped registers associated with this peripheral should have an
+/// address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and
+/// `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`.
+pub const TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES: usize = 0x20;
+
+/// MMIO Region
+///
+/// MMIO region excludes any memory that is separate from the module
+/// configuration space, i.e. ROM, main SRAM, and flash are excluded but
+/// retention SRAM, spi_device memory, or usbdev memory are included.
+pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x1000;
+pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0x20000;