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[hw,mbx,rtl] Move SOC_INTR_ADDR/DATA registers to the end
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A mailbox con either be a PCIe mailbox or a FW mailbox. In case of the
PCIe setting, the SOC reagisters 0x0 and 0x4 implement the capability
header functionality, but this is done outside of the mbx RTL. PCIe
mailboxes do not use the SOC_INTR_DATA/ADDR registers. FW-based
mailboxes on the other hand only use the SOC_INTR_DATA/ADDR registers
but no capability headers. Previously, it was decided to alias both
registers as they are used orthogonally. However, this deceission was
revised.

This PR moves the SOC_INTR_DATA/ADDR registers to the end of the SOC
register interface to not alias with any capability header registers
for PCIe mailboxes

Signed-off-by: Robert Schilling <[email protected]>
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@Razer6 @andreaskurth
Razer6 authored and andreaskurth committed Apr 29, 2024
1 parent ded45ac commit b3f0672
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Showing 3 changed files with 140 additions and 139 deletions.
61 changes: 31 additions & 30 deletions hw/ip/mbx/data/mbx.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -336,36 +336,7 @@
}
]
soc: [
{ name: "SOC_DOE_INTR_MSG_ADDR"
desc: '''
Utilized by the mailbox responder to send an interrupt message to the requester via a write to the configured address.
Defined only for FW-to-FW mailboxes.
'''
swaccess: "rw"
hwaccess: "hro"
fields: [
{ name: "doe_intr_msg_addr"
desc: "Utilized by the mailbox responder to send an interrupt message to the requester via a write to the configured address."
bits: "31:0"
resval: "0x0"
}
]
}
{ name: "SOC_DOE_INTR_MSG_DATA"
desc: '''
Interrupt message data to be sent to the address configured in the DOE_INTR_MSG_ADDR register.
Defined only for FW-to-FW mailboxes.
'''
swaccess: "rw"
hwaccess: "hro"
fields: [
{ name: "doe_intr_msg_data"
desc: "Interrupt message data to be sent to the address configured in the DOE_INTR_MSG_ADDR register."
bits: "31:0"
resval: "0x0"
}
]
}
{ skipto: "0x8" }
{ name: "SOC_CONTROL"
desc: "DOE mailbox control register."
hwaccess: "hrw"
Expand Down Expand Up @@ -482,6 +453,36 @@
swaccess: "rw"
}
}
{ name: "SOC_DOE_INTR_MSG_ADDR"
desc: '''
Utilized by the mailbox responder to send an interrupt message to the requester via a write to the configured address.
Defined only for FW-to-FW mailboxes.
'''
swaccess: "rw"
hwaccess: "hro"
fields: [
{ name: "doe_intr_msg_addr"
desc: "Utilized by the mailbox responder to send an interrupt message to the requester via a write to the configured address."
bits: "31:0"
resval: "0x0"
}
]
}
{ name: "SOC_DOE_INTR_MSG_DATA"
desc: '''
Interrupt message data to be sent to the address configured in the DOE_INTR_MSG_ADDR register.
Defined only for FW-to-FW mailboxes.
'''
swaccess: "rw"
hwaccess: "hro"
fields: [
{ name: "doe_intr_msg_data"
desc: "Interrupt message data to be sent to the address configured in the DOE_INTR_MSG_ADDR register."
bits: "31:0"
resval: "0x0"
}
]
}
]
}
}
42 changes: 21 additions & 21 deletions hw/ip/mbx/rtl/mbx_reg_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -286,14 +286,6 @@ package mbx_reg_pkg;
// Typedefs for registers for soc interface //
//////////////////////////////////////////////

typedef struct packed {
logic [31:0] q;
} mbx_reg2hw_soc_doe_intr_msg_addr_reg_t;

typedef struct packed {
logic [31:0] q;
} mbx_reg2hw_soc_doe_intr_msg_data_reg_t;

typedef struct packed {
struct packed {
logic q;
Expand Down Expand Up @@ -328,6 +320,14 @@ package mbx_reg_pkg;
} ready;
} mbx_reg2hw_soc_status_reg_t;

typedef struct packed {
logic [31:0] q;
} mbx_reg2hw_soc_doe_intr_msg_addr_reg_t;

typedef struct packed {
logic [31:0] q;
} mbx_reg2hw_soc_doe_intr_msg_data_reg_t;

typedef struct packed {
struct packed {
logic d;
Expand Down Expand Up @@ -368,10 +368,10 @@ package mbx_reg_pkg;

// Register -> HW type for soc interface
typedef struct packed {
mbx_reg2hw_soc_doe_intr_msg_addr_reg_t soc_doe_intr_msg_addr; // [75:44]
mbx_reg2hw_soc_doe_intr_msg_data_reg_t soc_doe_intr_msg_data; // [43:12]
mbx_reg2hw_soc_control_reg_t soc_control; // [11:4]
mbx_reg2hw_soc_status_reg_t soc_status; // [3:0]
mbx_reg2hw_soc_control_reg_t soc_control; // [75:68]
mbx_reg2hw_soc_status_reg_t soc_status; // [67:64]
mbx_reg2hw_soc_doe_intr_msg_addr_reg_t soc_doe_intr_msg_addr; // [63:32]
mbx_reg2hw_soc_doe_intr_msg_data_reg_t soc_doe_intr_msg_data; // [31:0]
} mbx_soc_reg2hw_t;

// HW -> register type for soc interface
Expand All @@ -381,10 +381,10 @@ package mbx_reg_pkg;
} mbx_soc_hw2reg_t;

// Register offsets for soc interface
parameter logic [SocAw-1:0] MBX_SOC_DOE_INTR_MSG_ADDR_OFFSET = 5'h 0;
parameter logic [SocAw-1:0] MBX_SOC_DOE_INTR_MSG_DATA_OFFSET = 5'h 4;
parameter logic [SocAw-1:0] MBX_SOC_CONTROL_OFFSET = 5'h 8;
parameter logic [SocAw-1:0] MBX_SOC_STATUS_OFFSET = 5'h c;
parameter logic [SocAw-1:0] MBX_SOC_DOE_INTR_MSG_ADDR_OFFSET = 5'h 18;
parameter logic [SocAw-1:0] MBX_SOC_DOE_INTR_MSG_DATA_OFFSET = 5'h 1c;

// Reset values for hwext registers and their fields for soc interface
parameter logic [31:0] MBX_SOC_CONTROL_RESVAL = 32'h 0;
Expand All @@ -403,18 +403,18 @@ package mbx_reg_pkg;

// Register index for soc interface
typedef enum int {
MBX_SOC_DOE_INTR_MSG_ADDR,
MBX_SOC_DOE_INTR_MSG_DATA,
MBX_SOC_CONTROL,
MBX_SOC_STATUS
MBX_SOC_STATUS,
MBX_SOC_DOE_INTR_MSG_ADDR,
MBX_SOC_DOE_INTR_MSG_DATA
} mbx_soc_id_e;

// Register width information to check illegal writes for soc interface
parameter logic [3:0] MBX_SOC_PERMIT [4] = '{
4'b 1111, // index[0] MBX_SOC_DOE_INTR_MSG_ADDR
4'b 1111, // index[1] MBX_SOC_DOE_INTR_MSG_DATA
4'b 1111, // index[2] MBX_SOC_CONTROL
4'b 1111 // index[3] MBX_SOC_STATUS
4'b 1111, // index[0] MBX_SOC_CONTROL
4'b 1111, // index[1] MBX_SOC_STATUS
4'b 1111, // index[2] MBX_SOC_DOE_INTR_MSG_ADDR
4'b 1111 // index[3] MBX_SOC_DOE_INTR_MSG_DATA
};

endpackage
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