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[rom_ctrl, rtl] Conditional coverage hole
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** There is a removal of an item (reqfifo_rvalid) from the conditional statement
   to deduct coverage hole 1011.We can't see dvalid & !reqfifo_rvalid. Reason
   being if d_valid is true then reqfifo_rvalid must be true. Similarly, if
   reqfifo_rvalid is false, then we can't see d_valid high.

** An assertion is added for the !reqfifo_rvalid -> !d_valid to make sure that it
   can never be true for the adapter.

Signed-off-by: Kinza Qamar <[email protected]>
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KinzaQamar committed Dec 11, 2024
1 parent 6460129 commit ae9a192
Showing 1 changed file with 3 additions and 1 deletion.
4 changes: 3 additions & 1 deletion hw/ip/tlul/rtl/tlul_adapter_sram.sv
Original file line number Diff line number Diff line change
Expand Up @@ -311,7 +311,7 @@ module tlul_adapter_sram
end

logic vld_rd_rsp;
assign vld_rd_rsp = d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead);
assign vld_rd_rsp = d_valid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead);
// If the response data is not valid, we set it to an illegal blanking value which is determined
// by whether the current transaction is an instruction fetch or a regular read operation.
logic [top_pkg::TL_DW-1:0] error_blanking_data;
Expand Down Expand Up @@ -682,4 +682,6 @@ module tlul_adapter_sram
`ASSERT_KNOWN(TlOutValidKnown_A, tl_o.d_valid)
`ASSERT(TlOutKnownIfFifoKnown_A, !$isunknown(rspfifo_rdata) -> !$isunknown(tl_o))

// The definition of d_valid leads to the assertion below.
`ASSERT(DValidNeedsReqFifoRValid, d_valid -> reqfifo_rvalid)
endmodule

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