Skip to content

Commit

Permalink
[ipgen,rstmgr] Fix englishbreakfast verilator build
Browse files Browse the repository at this point in the history
Signed-off-by: Guillermo Maturana <[email protected]>
  • Loading branch information
matutem committed Jan 12, 2024
1 parent 56ed9e5 commit 9b057e3
Show file tree
Hide file tree
Showing 7 changed files with 84 additions and 11 deletions.
28 changes: 25 additions & 3 deletions azure-pipelines.yml
Original file line number Diff line number Diff line change
Expand Up @@ -220,7 +220,9 @@ jobs:
echo -//quality/... >> "${TARGET_PATTERN_FILE}"
echo -//sw/otbn/crypto/... >> "${TARGET_PATTERN_FILE}"
echo -//third_party/riscv-compliance/... >> "${TARGET_PATTERN_FILE}"
echo -//hw:all >> "${TARGET_PATTERN_FILE}"
# echo -//hw:all >> "${TARGET_PATTERN_FILE}"
./bazelisk.sh query "deps(//hw:all_files)" | \
sed 's/\(.*\)/-\1/' >> "${TARGET_PATTERN_FILE}"
./bazelisk.sh cquery \
--noinclude_aspects \
--output=starlark \
Expand Down Expand Up @@ -291,8 +293,9 @@ jobs:
- job: chip_englishbreakfast_verilator
displayName: Verilated English Breakfast (Build)
# Build Verilator simulation of the English Breakfast toplevel design
dependsOn: lint
condition: and(succeeded(), eq(dependencies.lint.outputs['DetermineBuildType.onlyDocChanges'], '0'), eq(dependencies.lint.outputs['DetermineBuildType.onlyCdcChanges'], '0'))
dependsOn: checkout
# dependsOn: lint
# condition: and(succeeded(), eq(dependencies.lint.outputs['DetermineBuildType.onlyDocChanges'], '0'), eq(dependencies.lint.outputs['DetermineBuildType.onlyCdcChanges'], '0'))
pool:
vmImage: ubuntu-20.04
steps:
Expand All @@ -304,8 +307,27 @@ jobs:
verilator --version
verible-verilog-lint --version
displayName: Display environment
- bash: ci/scripts/build-chip-setup.sh englishbreakfast
displayName: Setup simulation with Verilator
# The repo should have all generated artifacts at this point.
- bash: |
ls $(Pipeline.Workspace)
ls $(Pipeline.Workspace)/opentitan-repo
- bash: |
tar -C $(Pipeline.Workspace)/opentitan-repo -czf $(Pipeline.Workspace)/opentitan-repo-with-obj.tar.gz .
# tar -czf $(Pipeline.Workspace)/opentitan-repo-with-obj.tar.gz .
displayName: Pack up repo_with_obj_dir
- publish: $(Pipeline.Workspace)/opentitan-repo-with-obj.tar.gz
artifact: repo-with-obj
displayName: Upload with_obj_dir
- bash: ci/scripts/build-chip-verilator.sh englishbreakfast
displayName: Build simulation with Verilator
- bash: |
tar -C $OBJ_DIR -czf $(Pipeline.Workspace)/obj_dir.tar.gz .
displayName: Pack up obj_dir
- publish: $(Pipeline.Workspace)/obj_dir.tar.gz .
artifact: obj-dir
displayName: Upload obj_dir
- template: ci/upload-artifacts-template.yml
parameters:
includePatterns:
Expand Down
48 changes: 48 additions & 0 deletions ci/scripts/build-chip-setup.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,48 @@
#!/bin/bash
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

# Build a chip-level verilator simulation
#
# Expects three arguments: the toplevel to build, the fusesoc core and
# the intermediate Verilated binary name

set -e

if [ $# != 1 ]; then
echo >&2 "Usage: build-chip-verilator.sh <toplevel>"
exit 1
fi
tl="$1"

case "$tl" in
earlgrey)
fileset=fileset_top
fusesoc_core=lowrisc:dv:chip_verilator_sim
;;
englishbreakfast)
fileset=fileset_topgen
fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator
# Englishbreakfast on CI runs on a 2-core CPU
util/topgen-fusesoc.py --files-root=. --topname=top_englishbreakfast
;;
*)
echo >&2 "Unknown toplevel: $tl"
exit 1
esac

# Move to project root
cd "$(git rev-parse --show-toplevel)"

. util/build_consts.sh

set -x

mkdir -p "$OBJ_DIR/hw"
mkdir -p "$BIN_DIR/hw/top_${tl}"

fusesoc --cores-root=. \
run --flag=$fileset --target=simple --setup \
--build-root="$OBJ_DIR/hw" \
$fusesoc_core
7 changes: 7 additions & 0 deletions hw/top_englishbreakfast/chip_englishbreakfast_verilator.core
Original file line number Diff line number Diff line change
Expand Up @@ -79,6 +79,12 @@ targets:
- files_sim_verilator
toplevel: chip_englishbreakfast_verilator

simple: &simple_target
toplevel: chip_englishbreakfast_verilator
filesets:
- files_sim_verilator
default_tool: vcs

sim:
parameters:
- PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
Expand All @@ -97,6 +103,7 @@ targets:
verilator:
mode: cc
verilator_options:
# - '-E'
# Disabling tracing reduces compile times but doesn't have a
# huge influence on runtime performance.
- '--trace'
Expand Down
2 changes: 1 addition & 1 deletion hw/top_englishbreakfast/data/top_englishbreakfast.hjson
Original file line number Diff line number Diff line change
Expand Up @@ -257,7 +257,7 @@
param_decl: {
SecCheck: "0",
}
attr: "templated",
attr: "ipgen",
},
{ name: "clkmgr_aon",
type: "clkmgr",
Expand Down
2 changes: 1 addition & 1 deletion hw/top_englishbreakfast/util/prepare_sw.py
Original file line number Diff line number Diff line change
Expand Up @@ -145,7 +145,7 @@ def main():
'ip/clkmgr/data/autogen/clkmgr.hjson',
'ip/flash_ctrl/data/autogen/flash_ctrl.hjson',
'ip_autogen/pwrmgr/data/pwrmgr.hjson',
'ip/rstmgr/data/autogen/rstmgr.hjson',
'ip_autogen/rstmgr/data/rstmgr.hjson',
'ip/pinmux/data/autogen/pinmux.hjson',
'ip_autogen/rv_plic/data/rv_plic.hjson',
'ip/ast/data/ast.hjson',
Expand Down
1 change: 0 additions & 1 deletion topgen-reg-only.core
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,6 @@ filesets:
- lowrisc:ip:clkmgr_reggen
- lowrisc:ip:flash_ctrl_reggen
- lowrisc:ip:pinmux_reggen
- lowrisc:ip:rstmgr_reggen

targets:
default: &default
Expand Down
7 changes: 2 additions & 5 deletions util/topgen-fusesoc.py
Original file line number Diff line number Diff line change
Expand Up @@ -75,11 +75,10 @@ def main():
'clkmgr': '',
'flash_ctrl': '_core',
'pinmux': '',
'rstmgr': '',
}

# reg-only
for ip in ['clkmgr', 'flash_ctrl', 'pinmux', 'rstmgr']:
for ip in ['clkmgr', 'flash_ctrl', 'pinmux']:
core_filepath = os.path.abspath(os.path.join(files_out, 'generated-%s.core' % ip))
name = 'lowrisc:ip:%s_reggen' % ip,
files = ['ip/%s/rtl/autogen/%s_reg_pkg.sv' % (ip, ip),
Expand Down Expand Up @@ -126,7 +125,7 @@ def main():
'lowrisc:prim:util',
'lowrisc:ip:lc_ctrl_pkg',
'lowrisc:ip:pwrmgr_pkg',
# rstmgr
'lowrisc:ip:rstmgr_pkg',
'lowrisc:prim:clock_mux2',
# clkmgr
'lowrisc:prim:all',
Expand All @@ -147,8 +146,6 @@ def main():
'ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv',
'ip/flash_ctrl/rtl/autogen/flash_ctrl.sv',
'ip/flash_ctrl/rtl/autogen/flash_ctrl_region_cfg.sv',
'ip/rstmgr/rtl/autogen/rstmgr_pkg.sv',
'ip/rstmgr/rtl/autogen/rstmgr.sv',
# Top
'rtl/autogen/%s_rnd_cnst_pkg.sv' % topname,
'rtl/autogen/%s_pkg.sv' % topname,
Expand Down

0 comments on commit 9b057e3

Please sign in to comment.