[sival,tests] Allow excessive csrng irqs in plic_all_irqs_test

Carefully allow these excessive irqs for the correct portion of the tests, addressing #20747 so this test passes. Add a TODO against the issue above so the code is adjusted depending on how the issue is addressed. Enable these tests in fpga_cw310_sival_rom_ext. Signed-off-by: Guillermo Maturana <[email protected]>
lowRISC · Jan 13, 2024 · 93cdae2 · 93cdae2
1 parent ff4673e
commit 93cdae2
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Showing 4 changed files with 750 additions and 772 deletions.
diff --git a/sw/device/tests/autogen/BUILD b/sw/device/tests/autogen/BUILD
@@ -16,66 +16,6 @@ load(
 
 package(default_visibility = ["//visibility:public"])
 
-# IP Integration Tests
-opentitan_test(
-    name = "plic_all_irqs_test_0".format(min),
-    srcs = ["plic_all_irqs_test.c"],
-    copts = [
-        "-DTEST_MIN_IRQ_PERIPHERAL=0",
-        "-DTEST_MAX_IRQ_PERIPHERAL=10",
-    ],
-    exec_env = {
-        "//hw/top_earlgrey:fpga_cw310_sival": None,
-        "//hw/top_earlgrey:fpga_cw310_test_rom": None,
-        "//hw/top_earlgrey:silicon_creator": None,
-        "//hw/top_earlgrey:silicon_owner_sival_rom_ext": "silicon_owner",
-        "//hw/top_earlgrey:sim_dv": None,
-        "//hw/top_earlgrey:sim_verilator": None,
-    },
-    silicon_owner = silicon_params(
-        # TODO(lowrisc/opentitan#20747): Enable silicon_owner when fixed.
-        tags = ["broken"],
-    ),
-    verilator = verilator_params(
-        timeout = "eternal",
-        tags = ["flaky"],
-        # often times out in 3600s on 4 cores
-    ),
-    deps = [
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
-        "//sw/device/lib/arch:boot_stage",
-        "//sw/device/lib/base:mmio",
-        "//sw/device/lib/dif:adc_ctrl",
-        "//sw/device/lib/dif:alert_handler",
-        "//sw/device/lib/dif:aon_timer",
-        "//sw/device/lib/dif:csrng",
-        "//sw/device/lib/dif:edn",
-        "//sw/device/lib/dif:entropy_src",
-        "//sw/device/lib/dif:flash_ctrl",
-        "//sw/device/lib/dif:gpio",
-        "//sw/device/lib/dif:hmac",
-        "//sw/device/lib/dif:i2c",
-        "//sw/device/lib/dif:keymgr",
-        "//sw/device/lib/dif:kmac",
-        "//sw/device/lib/dif:otbn",
-        "//sw/device/lib/dif:otp_ctrl",
-        "//sw/device/lib/dif:pattgen",
-        "//sw/device/lib/dif:pwrmgr",
-        "//sw/device/lib/dif:rv_plic",
-        "//sw/device/lib/dif:rv_timer",
-        "//sw/device/lib/dif:sensor_ctrl",
-        "//sw/device/lib/dif:spi_device",
-        "//sw/device/lib/dif:spi_host",
-        "//sw/device/lib/dif:sysrst_ctrl",
-        "//sw/device/lib/dif:uart",
-        "//sw/device/lib/dif:usbdev",
-        "//sw/device/lib/runtime:irq",
-        "//sw/device/lib/runtime:log",
-        "//sw/device/lib/testing:rv_plic_testutils",
-        "//sw/device/lib/testing/test_framework:ottf_main",
-    ],
-)
-
 [
     opentitan_test(
         name = "plic_all_irqs_test_{}".format(min),
@@ -86,6 +26,7 @@ opentitan_test(
         ],
         exec_env = {
             "//hw/top_earlgrey:fpga_cw310_sival": None,
+            "//hw/top_earlgrey:fpga_cw310_sival_rom_ext": None,
             "//hw/top_earlgrey:fpga_cw310_test_rom": None,
             "//hw/top_earlgrey:silicon_creator": None,
             "//hw/top_earlgrey:silicon_owner_sival_rom_ext": None,
@@ -131,7 +72,7 @@ opentitan_test(
             "//sw/device/lib/testing/test_framework:ottf_main",
         ],
     )
-    for min in range(10, 23, 10)
+    for min in range(0, 23, 10)
 ]
 
 test_suite(