[topgen] Generically filter for MMIO region visible devices

Add a new subspace entry to the address spaces to group multple address to the same address space. For this subspace, the range is computed and added as a definition to the C and Rust collateral. Signed-off-by: Robert Schilling <[email protected]>
lowRISC · Jun 5, 2024 · 93b29bb · 93b29bb
1 parent 3216fab
commit 93b29bb
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Showing 16 changed files with 357 additions and 136 deletions.
diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson
@@ -454,6 +454,63 @@
     {
       name: hart
       desc: The main address space, shared between the CPU and DM
+      subspaces:
+      [
+        {
+          name: mmio
+          desc:
+            '''
+            MMIO region excludes any memory that is separate from the module configuration
+            space, i.e. ROM, main SRAM, and mbx SRAM are excluded but retention SRAM or
+            spi_device are included.
+            '''
+          nodes:
+          [
+            uart0
+            gpio
+            spi_device
+            i2c0
+            rv_timer
+            otp_ctrl
+            lc_ctrl.regs
+            alert_handler
+            spi_host0
+            pwrmgr_aon
+            rstmgr_aon
+            clkmgr_aon
+            pinmux_aon
+            aon_timer_aon
+            ast
+            sensor_ctrl
+            soc_proxy.core
+            sram_ctrl_ret_aon
+            rv_plic
+            aes
+            hmac
+            otbn
+            keymgr_dpe
+            csrng
+            edn0
+            edn1
+            sram_ctrl_main.regs
+            sram_ctrl_mbox.regs
+            rom_ctrl0.regs
+            rom_ctrl1.regs
+            dma
+            mbx0.core
+            mbx1.core
+            mbx2.core
+            mbx3.core
+            mbx4.core
+            mbx5.core
+            mbx6.core
+            mbx_jtag.core
+            mbx_pcie0.core
+            mbx_pcie1.core
+            rv_core_ibex
+          ]
+        }
+      ]
     }
     {
       name: soc_mbx

diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson
@@ -166,7 +166,62 @@
   // all peripherals, though not every peripheral will be accessible to every
   // host in that address space--Access privileges are separate from addresses.
   addr_spaces: [
-    { name: "hart", desc: "The main address space, shared between the CPU and DM"},
+    { name: "hart"
+      desc: "The main address space, shared between the CPU and DM"
+      subspaces: [
+        { name: "mmio",
+          desc: '''
+                MMIO region excludes any memory that is separate from the module configuration
+                space, i.e. ROM, main SRAM, and mbx SRAM are excluded but retention SRAM or
+                spi_device are included.
+                '''
+          nodes: [
+            "uart0",
+            "gpio",
+            "spi_device",
+            "i2c0",
+            "rv_timer",
+            "otp_ctrl",
+            "lc_ctrl.regs",
+            "alert_handler",
+            "spi_host0",
+            "pwrmgr_aon",
+            "rstmgr_aon",
+            "clkmgr_aon",
+            "pinmux_aon",
+            "aon_timer_aon",
+            "ast"
+            "sensor_ctrl",
+            "soc_proxy.core",
+            "sram_ctrl_ret_aon",
+            "rv_plic",
+            "aes",
+            "hmac",
+            "otbn",
+            "keymgr_dpe"
+            "csrng",
+            "edn0",
+            "edn1",
+            "sram_ctrl_main.regs",
+            "sram_ctrl_mbox.regs",
+            "rom_ctrl0.regs",
+            "rom_ctrl1.regs",
+            "dma",
+            "mbx0.core",
+            "mbx1.core",
+            "mbx2.core",
+            "mbx3.core",
+            "mbx4.core",
+            "mbx5.core",
+            "mbx6.core",
+            "mbx_jtag.core",
+            "mbx_pcie0.core",
+            "mbx_pcie1.core",
+            "rv_core_ibex"
+          ],
+        },
+      ]
+    }
     { name: "soc_mbx", desc: "SoC address space for mailbox access"},
     { name: "soc_dbg", desc: "SoC address space for debug module interfaces"},
   ]

diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs
@@ -2745,7 +2745,7 @@ pub enum TopDarjeelingHintableClocks {
 /// MMIO Region
 ///
 /// MMIO region excludes any memory that is separate from the module
-/// configuration space, i.e. ROM, main SRAM, and flash are excluded but
-/// retention SRAM, spi_device memory, or usbdev memory are included.
+/// configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but
+/// retention SRAM or spi_device are included.
 pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x21100000;
-pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0xF400020;
+pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0xF501000;
diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_memory.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling_memory.rs
@@ -734,7 +734,7 @@ pub const TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES: usize = 0x800;
 /// MMIO Region
 ///
 /// MMIO region excludes any memory that is separate from the module
-/// configuration space, i.e. ROM, main SRAM, and flash are excluded but
-/// retention SRAM, spi_device memory, or usbdev memory are included.
+/// configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but
+/// retention SRAM or spi_device are included.
 pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x21100000;
-pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0xF400020;
+pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0xF501000;
diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling.h b/hw/top_darjeeling/sw/autogen/top_darjeeling.h
@@ -1675,8 +1675,8 @@ typedef enum top_darjeeling_hintable_clocks {
  * MMIO Region
  *
  * MMIO region excludes any memory that is separate from the module
- * configuration space, i.e. ROM, main SRAM, and flash are excluded but
- * retention SRAM, spi_device memory, or usbdev memory are included.
+ * configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but
+ * retention SRAM or spi_device are included.
  */
 #define TOP_DARJEELING_MMIO_BASE_ADDR 0x21100000u
 #define TOP_DARJEELING_MMIO_SIZE_BYTES 0xF501000u

diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h
@@ -983,8 +983,8 @@
  * MMIO Region
  *
  * MMIO region excludes any memory that is separate from the module
- * configuration space, i.e. ROM, main SRAM, and flash are excluded but
- * retention SRAM, spi_device memory, or usbdev memory are included.
+ * configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but
+ * retention SRAM or spi_device are included.
  */
 #define TOP_DARJEELING_MMIO_BASE_ADDR 0x21100000
 #define TOP_DARJEELING_MMIO_SIZE_BYTES 0xF501000

diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -524,6 +524,64 @@
     {
       name: hart
       desc: The main address space, shared between the CPU and DM
+      subspaces:
+      [
+        {
+          name: mmio
+          desc:
+            '''
+            MMIO region excludes any memory that is separate from the module configuration
+            space, i.e. ROM, main SRAM, and flash are excluded but retention SRAM, spi_device
+            memory, or usbdev memory are included.
+            '''
+          nodes:
+          [
+            uart0
+            uart1
+            uart2
+            uart3
+            gpio
+            spi_device
+            i2c0
+            i2c1
+            i2c2
+            pattgen
+            rv_timer
+            otp_ctrl
+            lc_ctrl
+            alert_handler
+            spi_host0
+            spi_host1
+            usbdev
+            pwrmgr_aon
+            rstmgr_aon
+            clkmgr_aon
+            sysrst_ctrl_aon
+            adc_ctrl_aon
+            pwm_aon
+            pinmux_aon
+            aon_timer_aon
+            ast
+            sensor_ctrl
+            sram_ctrl_ret_aon
+            flash_ctrl.core
+            flash_ctrl.prim
+            rv_plic
+            aes
+            hmac
+            kmac
+            otbn
+            keymgr
+            csrng
+            entropy_src
+            edn0
+            edn1
+            sram_ctrl_main.regs
+            rom_ctrl0.regs
+            rv_core_ibex
+          ]
+        }
+      ]
     }
   ]
   module:

diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -171,7 +171,63 @@
   // all peripherals, though not every peripheral will be accessible to every
   // host in that address space--Access privileges are separate from addresses.
   addr_spaces: [
-    { name: "hart", desc: "The main address space, shared between the CPU and DM"},
+    { name: "hart",
+      desc: "The main address space, shared between the CPU and DM"
+      subspaces: [
+        { name: "mmio",
+          desc: '''
+                MMIO region excludes any memory that is separate from the module configuration
+                space, i.e. ROM, main SRAM, and flash are excluded but retention SRAM, spi_device
+                memory, or usbdev memory are included.
+                '''
+          nodes: [
+            "uart0",
+            "uart1",
+            "uart2",
+            "uart3",
+            "gpio",
+            "spi_device",
+            "i2c0",
+            "i2c1",
+            "i2c2",
+            "pattgen",
+            "rv_timer"
+            "otp_ctrl",
+            "lc_ctrl",
+            "alert_handler",
+            "spi_host0",
+            "spi_host1",
+            "usbdev",
+            "pwrmgr_aon",
+            "rstmgr_aon",
+            "clkmgr_aon",
+            "sysrst_ctrl_aon",
+            "adc_ctrl_aon",
+            "pwm_aon",
+            "pinmux_aon",
+            "aon_timer_aon",
+            "ast",
+            "sensor_ctrl",
+            "sram_ctrl_ret_aon",
+            "flash_ctrl.core",
+            "flash_ctrl.prim",
+            "rv_plic",
+            "aes",
+            "hmac",
+            "kmac",
+            "otbn",
+            "keymgr",
+            "csrng",
+            "entropy_src",
+            "edn0"
+            "edn1",
+            "sram_ctrl_main.regs"
+            "rom_ctrl0.regs",
+            "rv_core_ibex"
+          ]
+        }
+      ]
+    },
   ]
 
   // `module` defines the peripherals.

diff --git a/util/topgen/c.py b/util/topgen/c.py
@@ -10,32 +10,11 @@
 from mako.template import Template
 from reggen.ip_block import IpBlock
 
-from .lib import Name, get_base_and_size
+from .lib import Name, get_base_and_size, MemoryRegion, init_subranges
 
 C_FILE_EXTENSIONS = (".c", ".h", ".cc", ".inc")
 
 
-class MemoryRegion(object):
-    def __init__(self, name: Name, base_addr: int, size_bytes: int):
-        assert isinstance(base_addr, int)
-        self.name = name
-        self.base_addr = base_addr
-        self.size_bytes = size_bytes
-        self.size_words = (size_bytes + 3) // 4
-
-    def base_addr_name(self):
-        return self.name + Name(["base", "addr"])
-
-    def offset_name(self):
-        return self.name + Name(["offset"])
-
-    def size_bytes_name(self):
-        return self.name + Name(["size", "bytes"])
-
-    def size_words_name(self):
-        return self.name + Name(["size", "words"])
-
-
 class CEnum(object):
     def __init__(self, name):
         self.name = name
@@ -123,7 +102,7 @@ def __init__(self, top_info, name_to_block: Dict[str, IpBlock]):
         self._init_rstmgr_sw_rsts()
         self._init_pwrmgr_reset_requests()
         self._init_clkmgr_clocks()
-        self._init_mmio_region()
+        self.subranges = init_subranges(self.top, self._top_name, self.devices(), self.addr_space)
 
     def devices(self) -> List[Tuple[Tuple[str, Optional[str]], MemoryRegion]]:
         '''Return a list of MemoryRegion objects for devices on the bus
@@ -510,30 +489,3 @@ def _init_clkmgr_clocks(self):
 
         self.clkmgr_gateable_clocks = gateable_clocks
         self.clkmgr_hintable_clocks = hintable_clocks
-
-    def _init_mmio_region(self):
-        """
-        Computes the bounds of the MMIO region.
-
-        MMIO region excludes any memory that is separate from the module configuration
-        space, i.e. ROM, main SRAM, and flash are excluded but retention SRAM,
-        spi_device memory, or usbdev memory are included.
-        """
-        memories = [region.base_addr for (_, region) in self.memories()]
-        # TODO(#14345): Remove the hardcoded "rv_dm" name check below.
-        # TODO: we need a cleaner way to define which buses are visible
-        # by the CPU and which ones are not. For now, exclude every
-        # interface with the name `dbg`, since that is attached to the
-        # debug bus which is not connected to the CPU LSU.
-        regions = [
-            region for ((dev_name, if_name), region) in self.devices()
-            if (dev_name == "sram_ctrl_ret_aon" and if_name == 'ram') or
-               (region.base_addr not in memories and dev_name != "rv_dm" and
-                (if_name is None or if_name != 'dbg'))
-        ]
-        # Note: The memory interface of the retention RAM is in the MMIO address space,
-        # which we prefer since it reduces the number of ePMP regions we need.
-        mmio = range(min([r.base_addr for r in regions]),
-                     max([r.base_addr + r.size_bytes for r in regions]))
-        self.mmio = MemoryRegion(self._top_name + Name(["mmio"]), mmio.start,
-                                 mmio.stop - mmio.start)