[openocd,opentitanlib] Add Earlgrey chip tapID

Earlgrey has the TapID in this file and fixes errors in init.

util/openocd/target/lowrisc-earlgrey-silicon.cfg

@@ -0,0 +1,45 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Target configuration for the lowRISC "Earl Grey" chip
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME riscv
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # Defined in `hw/top_earlgrey/rtl/jtag_id_pkg.sv`.
+   set _CPUTAPID 0x108c185b
+}
+
+jtag newtap $_CHIPNAME tap -irlen 5 -expected-id $_CPUTAPID
+set _TARGETNAME $_CHIPNAME.tap
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
+
+# Configure work area in on-chip SRAM
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 1000 -work-area-backup 0
+
+# This chip implements system bus access, use it.
+# Accessing the memory through the system bus is faster than through
+# instruction feeding.
+riscv set_mem_access sysbus
+
+# Expose custom CSRs, cpuctrl and secureseed
+# See https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html
+riscv expose_csrs 1984=cpuctrl,1985=secureseed
+
+# Be verbose about GDB errors
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Always use hardware breakpoints. Since we don't use `flash bank` commands,
+# OpenOCD won't provide a memory map to GDB. This means that GDB isn't be aware
+# that the code resides in a read-only memory, and therefore should use hardware
+# breakpoints. This setting makes OpenOCD convert the software breakpoints into
+# hardware ones.
+gdb_breakpoint_override hard