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Signed-off-by: Amaury Pouly <[email protected]>
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pamaury committed Nov 28, 2024
1 parent 4da3f37 commit 8c28693
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Showing 59 changed files with 569 additions and 225 deletions.
16 changes: 16 additions & 0 deletions hw/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -5,12 +5,15 @@
load("@rules_pkg//pkg:mappings.bzl", "pkg_files")
load("//rules:fusesoc.bzl", "fusesoc_build")

package(default_visibility = ["//visibility:public"])

# This configuration exposes fusesoc's "verilator_options" option to the
# command line. This is intended to allow CI to specifically build a single
# -threaded Verilated model to suit it's resource constraints.
# By default, the Verilated model should be built to
# run with 4 threads.
load("@bazel_skylib//rules:common_settings.bzl", "string_list_flag")
load("//hw/top:defs.bzl", "opentitan_select_top")

string_list_flag(
name = "verilator_options",
Expand All @@ -20,6 +23,19 @@ string_list_flag(
],
)

# HACK
# This alias points to the correct sim_dv execution environment based on the top.
[
alias(
name = env,
actual = opentitan_select_top({
"earlgrey": "//hw/top_earlgrey:{}".format(env),
"darjeeling": "//hw/top_darjeeling:{}".format(env),
}, "//invalid/top"),
)
for env in ["sim_dv_base", "sim_dv"]
]

# This configuration exposes fusesoc's "make_options" to enable parallel
# compilation of the verilated model. Compilation takes about 30m of cpu time
# and 5m of time that isn't parallelized by this option, so this should reduce
Expand Down
20 changes: 19 additions & 1 deletion hw/top/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
# SPDX-License-Identifier: Apache-2.0

load("@bazel_skylib//rules:common_settings.bzl", "string_flag")
load("//rules/opentitan:hw.bzl", "select_top", "select_top_lib")
load("//rules/opentitan:hw.bzl", "select_top", "select_top_lib", "select_top_ld")
load("//rules/opentitan:util.bzl", "flatten")
load(
"//rules:autogen.bzl",
Expand Down Expand Up @@ -71,6 +71,24 @@ alias(
}),
)

[
select_top_ld(
name = "top_{}_ld".format(top),
all_tops = ALL_TOPS,
top = top,
)
for top in ALL_TOP_NAMES
]

# Point to the right top library.
alias(
name = "top_ld",
actual = select({
"is_{}".format(top): ":top_{}_ld".format(top)
for top in ALL_TOP_NAMES
}),
)

[
opentitan_ip_c_header(
name = "{}_c_regs".format(ip),
Expand Down
91 changes: 91 additions & 0 deletions hw/top_darjeeling/BUILD
Original file line number Diff line number Diff line change
@@ -0,0 +1,91 @@
# Copyright lowRISC contributors (OpenTitan project).
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

load(
"//rules/opentitan:defs.bzl",
"DEFAULT_TEST_FAILURE_MSG",
"DEFAULT_TEST_SUCCESS_MSG",
"sim_dv",
)

package(default_visibility = ["//visibility:public"])

###########################################################################
# Sim DV Environments
#
# The sim_dv_base target is only meant to be used for building ROMs and
# other items without `testonly=True`.
###########################################################################

# Remark: we must use a different name from earlgrey because the test point
# names are derived from the exec_env's target named
sim_dv(
name = "sim_dv_base",
design = "darjeeling",
exec_env = "sim_dv",
extract_sw_logs = "//util/device_sw_utils:extract_sw_logs_db",
flash_scramble_tool = "//util/design:gen-flash-img",
libs = [
"//sw/device/lib/arch:boot_stage_rom_ext",
"//sw/device/lib/arch:sim_dv",
],
linker_script = "//sw/device/lib/testing/test_framework:ottf_ld_silicon_creator_slot_a",
rom_scramble_config = "//hw/top_darjeeling/data/autogen:top_darjeeling.gen.hjson",
)

sim_dv(
name = "sim_dv",
testonly = True,
base = ":sim_dv_base",
exec_env = "sim_dv",
# rom = "//sw/device/lib/testing/test_rom:test_rom",
)

# Initial list of DV sims required by Robert, extracted
# from the DV testplan.
test_suite(
name = "initial_test_list",
tests = [
"//sw/device/tests:otbn_randomness_test_sim_dv",
"//sw/device/tests:pwrmgr_random_sleep_all_reset_reqs_test_sim_dv",
"//sw/device/tests:rstmgr_alert_info_test_sim_dv",
"//sw/device/tests:rstmgr_cpu_info_test_sim_dv",
"//sw/device/tests:rstmgr_sw_req_test_sim_dv",
"//sw/device/tests:rstmgr_sw_rst_ctrl_test_sim_dv",
"//sw/device/tests:rv_core_ibex_nmi_irq_test_sim_dv",
"//sw/device/tests:rv_core_ibex_rnd_test_sim_dv",
"//sw/device/tests/sim_dv:alert_handler_lpg_sleep_mode_alerts_test_sim_dv",
],
)

test_suite(
name = "initial_test_list2",
tests = [
# base_rom_e2e_smoke?
"//sw/device/tests/autogen:plic_all_irqs_test_0_sim_dv",
"//sw/device/tests/autogen:plic_all_irqs_test_10_sim_dv",
"//sw/device/tests/autogen:plic_all_irqs_test_20_sim_dv",
# "//sw/device/tests:rv_dm_lc_disabled_tl_sim_dv",
# "//sw/device/tests:rv_dm_lc_disabled_jtag_sim_dv",
"//sw/device/tests:kmac_app_rom_test_sim_dv",
"//sw/device/tests:rstmgr_sw_rst_ctrl_test_sim_dv",
"//sw/device/tests:hmac_enc_test_sim_dv",
"//sw/device/tests:clkmgr_jitter_test_sim_dv",
"//sw/device/tests/sim_dv:rom_ctrl_integrity_check_test_sim_dv",
"//sw/device/tests:aes_entropy_test_sim_dv",
"//sw/device/tests:kmac_idle_test_sim_dv",
"//sw/device/tests:kmac_mode_cshake_test_sim_dv",
"//sw/device/tests:kmac_mode_kmac_test_sim_dv",
"//sw/device/tests/sim_dv:lc_ctrl_scrap_test_sim_dv",
"//sw/device/tests:sleep_pin_mio_dio_val_test_sim_dv",
],
)

test_suite(
name = "initial_test_list3",
tests = [
"//sw/device/tests:power_virus_systemtest_sim_dv",
],
)

1 change: 1 addition & 0 deletions hw/top_darjeeling/data/autogen/defs.bzl
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,7 @@ DARJEELING = opentitan_top(
name = "darjeeling",
hjson = "//hw/top_darjeeling/data/autogen:top_darjeeling.gen.hjson",
top_lib = "//hw/top_darjeeling/sw/autogen:top_darjeeling",
top_ld = "//hw/top_darjeeling/sw/autogen:top_darjeeling_memory",
ips = [
AES,
ALERT_HANDLER,
Expand Down
4 changes: 2 additions & 2 deletions hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld
Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,8 @@ MEMORY {
ram_mbox(rwx) : ORIGIN = 0x11000000, LENGTH = 0x1000
rom0(rx) : ORIGIN = 0x00008000, LENGTH = 0x8000
rom1(rx) : ORIGIN = 0x00020000, LENGTH = 0x10000
rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = None
owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = None
rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = 0x80000
owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = 0x80000
}

/**
Expand Down
1 change: 1 addition & 0 deletions hw/top_earlgrey/data/autogen/defs.bzl
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,7 @@ EARLGREY = opentitan_top(
name = "earlgrey",
hjson = "//hw/top_earlgrey/data/autogen:top_earlgrey.gen.hjson",
top_lib = "//hw/top_earlgrey/sw/autogen:top_earlgrey",
top_ld = "//hw/top_earlgrey/sw/autogen:top_earlgrey_memory",
ips = [
ADC_CTRL,
AES,
Expand Down
4 changes: 4 additions & 0 deletions rules/host.bzl
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,9 @@ def _host_tools_transition_impl(settings, attr):
"//hw/bitstream/universal:rom": "//hw/bitstream/universal:none",
"//hw/bitstream/universal:otp": "//hw/bitstream/universal:none",
"//hw/bitstream/universal:env": "//hw/bitstream/universal:none",
# WARNING This is a horrible hack: when we transition to host, we pretend
# that this is earlgrey so opentitantool can compile...
"//hw/top": "earlgrey",
}
return ret

Expand All @@ -39,5 +42,6 @@ host_tools_transition = transition(
"//hw/bitstream/universal:rom",
"//hw/bitstream/universal:otp",
"//hw/bitstream/universal:env",
"//hw/top",
],
)
31 changes: 28 additions & 3 deletions rules/linker.bzl
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,23 @@
"""Rules for declaring linker scripts and linker script fragments."""

def _ld_library_impl(ctx):
files = [] + ctx.files.includes
substitutions = {
key: ctx.expand_location(subst)
for (key, subst) in ctx.attr.substitutions.items()
}

def get_file(f):
if ctx.attr.substitutions == {}:
return f
fout = ctx.actions.declare_file(ctx.label.name + "_" + f.basename)
ctx.actions.expand_template(
template = f,
output = fout,
substitutions = substitutions,
)
return fout

files = [get_file(f) for f in ctx.files.includes]
user_link_flags = []

# Disable non-volatile scratch region and counters if building for english
Expand All @@ -21,12 +37,15 @@ def _ld_library_impl(ctx):
]

if ctx.file.script:
files += ctx.files.script
files.append(get_file(ctx.file.script))
user_link_flags += [
"-Wl,-T,{}".format(ctx.file.script.path),
"-Wl,-T,{}".format(files[-1].path),
]

return [
DefaultInfo(
files = depset(files),
),
cc_common.merge_cc_infos(
direct_cc_infos = [CcInfo(
linking_context = cc_common.create_linking_context(
Expand Down Expand Up @@ -57,6 +76,10 @@ ld_library = rule(
alignment for segments and not to include the headers in the first segment
(this is the -nmagic option of GNU ld). See https://reviews.llvm.org/D61201
for more details.
If the substitution dictionary is not empty, the content of the file will
be expanded using bazel's `actions.expand_template`. If some substitutions
refer to label not present in `deps`, they need to be added to `subst_deps`.
""",
attrs = {
"script": attr.label(allow_single_file = True),
Expand All @@ -71,5 +94,7 @@ ld_library = rule(
"non_page_aligned_segments": attr.bool(
default = False,
),
"substitutions": attr.string_dict(),
"subst_deps": attr.label_list()
},
)
4 changes: 3 additions & 1 deletion rules/opentitan/defs.bzl
Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,9 @@ opentitan_manual_test = _opentitan_manual_test
EARLGREY_TEST_ENVS = {
"//hw/top_earlgrey:fpga_cw310_sival_rom_ext": None,
"//hw/top_earlgrey:fpga_cw310_rom_with_fake_keys": None,
"//hw/top_earlgrey:sim_dv": None,
# "//hw/top_earlgrey:sim_dv": None,
# HACK
"//hw:sim_dv": None,
"//hw/top_earlgrey:sim_verilator": None,
}

Expand Down
16 changes: 15 additions & 1 deletion rules/opentitan/hw.bzl
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ def opentitan_ip(name, hjson):
hjson = hjson,
)

def opentitan_top(name, hjson, top_lib, ips):
def opentitan_top(name, hjson, top_lib, top_ld, ips):
"""
Return a structure describing a top.
Expand All @@ -32,6 +32,7 @@ def opentitan_top(name, hjson, top_lib, ips):
name = name,
hjson = hjson,
top_lib = top_lib,
top_ld = top_ld,
ips = ips,
)

Expand Down Expand Up @@ -124,3 +125,16 @@ def select_top_lib(name, all_tops, top):
name = name,
actual = libs[0],
)

def select_top_ld(name, all_tops, top):
"""
Create an alias to the top library.
"""
libs = [_top.top_ld for _top in all_tops if _top.name == top]
if len(libs) == 0:
fail("not top found with name {}".format(top))

native.alias(
name = name,
actual = libs[0],
)
2 changes: 1 addition & 1 deletion sw/device/examples/sram_program/sram_program.ld
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ OUTPUT_ARCH(riscv);
*/
__DYNAMIC = 0;

INCLUDE hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
INCLUDE top_memory.ld

_stack_end = ORIGIN(ram_main) + LENGTH(ram_main);

Expand Down
2 changes: 1 addition & 1 deletion sw/device/lib/arch/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -89,7 +89,7 @@ cc_library(
":device",
"//hw/top:rv_core_ibex_c_regs",
"//hw/top:uart_c_regs",
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
"//hw/top:top_lib",
],
)

Expand Down
17 changes: 12 additions & 5 deletions sw/device/lib/arch/device_sim_dv.c
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,19 @@

#include "sw/device/lib/arch/device.h"

#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
#include "rv_core_ibex_regs.h"
#include "uart_regs.h"

#if defined(OPENTITAN_IS_EARLGREY)
#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
#define RV_CORE_IBEX_CFG_BASE_ADDR TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR
#elif defined(OPENTITAN_IS_DARJEELING)
#include "hw/top_darjeeling/sw/autogen/top_darjeeling.h"
#define RV_CORE_IBEX_CFG_BASE_ADDR TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR
#else
#error unsupported top
#endif

/**
* Device-specific symbol definitions for the DV simulation device.
*/
Expand Down Expand Up @@ -58,11 +67,9 @@ const uint32_t kAstCheckPollCpuCycles =
CALCULATE_AST_CHECK_POLL_CPU_CYCLES(kClockFreqCpuHz);

const uintptr_t kDeviceTestStatusAddress =
TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR +
RV_CORE_IBEX_DV_SIM_WINDOW_REG_OFFSET;
RV_CORE_IBEX_CFG_BASE_ADDR + RV_CORE_IBEX_DV_SIM_WINDOW_REG_OFFSET;

const uintptr_t kDeviceLogBypassUartAddress =
TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR +
RV_CORE_IBEX_DV_SIM_WINDOW_REG_OFFSET + 0x04;
RV_CORE_IBEX_CFG_BASE_ADDR + RV_CORE_IBEX_DV_SIM_WINDOW_REG_OFFSET + 0x04;

void device_fpga_version_print(void) {}
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