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[entropy_src,doc] Fix some double spaces in markdown docs
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No big deal, but they jumped out at me a bit when I was looking for
something else in the source. This small patch fixes all the examples
that I found with:

    git grep -i '[a-z.]   *[a-z]' 'hw/ip/entropy_src/*.md'

Signed-off-by: Rupert Swarbrick <[email protected]>
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rswarbrick committed Dec 24, 2023
1 parent 671f2b5 commit 88eb813
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Showing 2 changed files with 14 additions and 14 deletions.
2 changes: 1 addition & 1 deletion hw/ip/entropy_src/doc/interfaces.md
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Expand Up @@ -13,7 +13,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt
| Port Name | Package::Struct | Type | Act | Width | Description |
|:---------------------------|:-----------------------------------|:--------|:------|--------:|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| entropy_src_hw_if | entropy_src_pkg::entropy_src_hw_if | req_rsp | rsp | 1 | |
| cs_aes_halt | entropy_src_pkg::cs_aes_halt | req_rsp | req | 1 | Coordinate activity between CSRNG's AES and Entropy Source's SHA3. The idea is that Entropy Source requests CSRNG's AES to halt and waits for CSRNG to acknowledge before it starts its SHA3. While SHA3 runs, Entropy Source keeps the request high. CSRNG may not drop the acknowledge before Entropy Source drops the request. Current limitations: 1. During startup and in Firmware Override - Extract & Insert mode, Entropy Source makes no AES Halt requests but still activates its SHA3 engine. 2. Outside Firmware Override - Extract & Insert mode, Entropy Source may activate its SHA3 engine without requesting AES Halt, but no more than for 24 Keccak rounds (24 clock cycles) every 512 clock cycles. |
| cs_aes_halt | entropy_src_pkg::cs_aes_halt | req_rsp | req | 1 | Coordinate activity between CSRNG's AES and Entropy Source's SHA3. The idea is that Entropy Source requests CSRNG's AES to halt and waits for CSRNG to acknowledge before it starts its SHA3. While SHA3 runs, Entropy Source keeps the request high. CSRNG may not drop the acknowledge before Entropy Source drops the request. Current limitations: 1. During startup and in Firmware Override - Extract & Insert mode, Entropy Source makes no AES Halt requests but still activates its SHA3 engine. 2. Outside Firmware Override - Extract & Insert mode, Entropy Source may activate its SHA3 engine without requesting AES Halt, but no more than for 24 Keccak rounds (24 clock cycles) every 512 clock cycles. |
| entropy_src_rng | entropy_src_pkg::entropy_src_rng | req_rsp | req | 1 | |
| entropy_src_xht | entropy_src_pkg::entropy_src_xht | req_rsp | req | 1 | |
| otp_en_entropy_src_fw_read | prim_mubi_pkg::mubi8 | uni | rcv | 1 | |
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26 changes: 13 additions & 13 deletions hw/ip/entropy_src/doc/registers.md
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Expand Up @@ -861,7 +861,7 @@ Repetition count test failure counter register

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:-------------------|:-----------------------------------------------------------------------------------------------------------------------------|
| 31:0 | ro | x | REPCNT_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
| 31:0 | ro | x | REPCNT_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |

## REPCNTS_TOTAL_FAILS
Repetition count symbol test failure counter register
Expand All @@ -877,7 +877,7 @@ Repetition count symbol test failure counter register

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:--------------------|:-----------------------------------------------------------------------------------------------------------------------------|
| 31:0 | ro | x | REPCNTS_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
| 31:0 | ro | x | REPCNTS_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |

## ADAPTP_HI_TOTAL_FAILS
Adaptive proportion high test failure counter register
Expand All @@ -893,7 +893,7 @@ Adaptive proportion high test failure counter register

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:----------------------|:-----------------------------------------------------------------------------------------------------------------------------|
| 31:0 | ro | x | ADAPTP_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
| 31:0 | ro | x | ADAPTP_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |

## ADAPTP_LO_TOTAL_FAILS
Adaptive proportion low test failure counter register
Expand All @@ -909,7 +909,7 @@ Adaptive proportion low test failure counter register

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:----------------------|:-----------------------------------------------------------------------------------------------------------------------------|
| 31:0 | ro | x | ADAPTP_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
| 31:0 | ro | x | ADAPTP_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |

## BUCKET_TOTAL_FAILS
Bucket test failure counter register
Expand All @@ -925,7 +925,7 @@ Bucket test failure counter register

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:-------------------|:-----------------------------------------------------------------------------------------------------------------------------|
| 31:0 | ro | x | BUCKET_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
| 31:0 | ro | x | BUCKET_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |

## MARKOV_HI_TOTAL_FAILS
Markov high test failure counter register
Expand All @@ -941,7 +941,7 @@ Markov high test failure counter register

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:----------------------|:-----------------------------------------------------------------------------------------------------------------------------|
| 31:0 | ro | x | MARKOV_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
| 31:0 | ro | x | MARKOV_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |

## MARKOV_LO_TOTAL_FAILS
Markov low test failure counter register
Expand All @@ -957,7 +957,7 @@ Markov low test failure counter register

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:----------------------|:-----------------------------------------------------------------------------------------------------------------------------|
| 31:0 | ro | x | MARKOV_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
| 31:0 | ro | x | MARKOV_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |

## EXTHT_HI_TOTAL_FAILS
External health test high threshold failure counter register
Expand All @@ -973,7 +973,7 @@ External health test high threshold failure counter register

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:---------------------|:-----------------------------------------------------------------------------------------------------------------------------|
| 31:0 | ro | x | EXTHT_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
| 31:0 | ro | x | EXTHT_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |

## EXTHT_LO_TOTAL_FAILS
External health test low threshold failure counter register
Expand All @@ -989,7 +989,7 @@ External health test low threshold failure counter register

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:---------------------|:-----------------------------------------------------------------------------------------------------------------------------|
| 31:0 | ro | x | EXTHT_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
| 31:0 | ro | x | EXTHT_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |

## ALERT_THRESHOLD
Alert threshold register
Expand All @@ -1004,10 +1004,10 @@ Alert threshold register
{"reg": [{"name": "ALERT_THRESHOLD", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "ALERT_THRESHOLD_INV", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
```

| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:--------------------|:-----------------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | rw | 0xfffd | ALERT_THRESHOLD_INV | This should be set to the value above, but inverted. |
| 15:0 | rw | 0x2 | ALERT_THRESHOLD | This is the threshold size that will signal an alert when value is reached. A value of zero will disable alerts. The default value is 2. |
| Bits | Type | Reset | Name | Description |
|:------:|:------:|:-------:|:--------------------|:-----------------------------------------------------------------------------------------------------------------------------------------|
| 31:16 | rw | 0xfffd | ALERT_THRESHOLD_INV | This should be set to the value above, but inverted. |
| 15:0 | rw | 0x2 | ALERT_THRESHOLD | This is the threshold size that will signal an alert when value is reached. A value of zero will disable alerts. The default value is 2. |

## ALERT_SUMMARY_FAIL_COUNTS
Alert summary failure counts register
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