Update lowrisc_ibex to lowRISC/ibex@667fd20d

Update code from upstream repository https://github.com/lowRISC/ibex.git to revision 667fd20d2ede51caececccbcbda3652074424ce2 * [rtl] Fix non-DSP reset in ibex_counter (Pascal Nasahl) * Revert "[rtl] Fix counter reset value on FPGA" (Pascal Nasahl) * [rtl] Fix counter reset value on FPGA (Pascal Nasahl) * [ci] remove Azure Pipelines (Gary Guo) Signed-off-by: Pascal Nasahl <[email protected]>
lowRISC · Dec 8, 2024 · 7ed46b1 · 7ed46b1
1 parent 937cb67
commit 7ed46b1
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Showing 3 changed files with 27 additions and 19 deletions.
diff --git a/hw/vendor/lowrisc_ibex.lock.hjson b/hw/vendor/lowrisc_ibex.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/lowRISC/ibex.git
-    rev: 84232a5bfa8b020cd05718b2ae21d8584c942df8
+    rev: 667fd20d2ede51caececccbcbda3652074424ce2
   }
 }
diff --git a/hw/vendor/lowrisc_ibex/doc/03_reference/verification_stages.rst b/hw/vendor/lowrisc_ibex/doc/03_reference/verification_stages.rst
@@ -84,7 +84,7 @@ V2 Checklist
 +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 | Tests         | SIM_FW_SIMULATED                    | N/A        | No ROM or firmware present.                                                                                                                                          |
 +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-| Regression    | SIM_NIGHTLY_REGRESSION_V2           | Complete   | Regression run in Azure pipeline only accessible to OpenTitan members.                                                                                               |
+| Regression    | SIM_NIGHTLY_REGRESSION_V2           | Complete   | Regression run in GitHub Actions only accessible to OpenTitan members.                                                                                               |
 |               |                                     |            | Publicly viewable reports on the `OpenTitan regression dashboard <https://reports.opentitan.org/hw/top_earlgrey/dv/summary/latest/report.html>`_ are planned for V3. |
 +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 | Coverage      | SIM_CODE_COVERAGE_V2                | Complete   | Coverage results available in nightly regression run.                                                                                                                |

diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv
@@ -51,27 +51,38 @@ module ibex_counter #(
   end
 
 `ifdef FPGA_XILINX
-  // Set DSP pragma for supported xilinx FPGAs
-  localparam int DspPragma = CounterWidth < 49 ? "yes" : "no";
-  (* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q;
-
-  // DSP output register requires synchronous reset.
-  `define COUNTER_FLOP_RST posedge clk_i
+  // On Xilinx FPGAs, 48-bit DSPs are available that can be used for the
+  // counter. Hence, use Xilinx specific flop implementation. The datatype for
+  // UseDsp is on purpose int as with string Xilinx throws an error for the
+  // use_dsp pragma.
+  localparam int UseDsp = CounterWidth < 49 ? "yes" : "no";
+  (* use_dsp = UseDsp *) logic [CounterWidth-1:0] counter_q;
 `else
+  localparam int UseDsp = "no";
   logic [CounterWidth-1:0] counter_q;
-
-  `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni
 `endif
 
-  // Counter flop
-  always_ff @(`COUNTER_FLOP_RST) begin
-    if (!rst_ni) begin
-      counter_q <= '0;
-    end else begin
-      counter_q <= counter_d;
+  if (UseDsp == "yes") begin : g_cnt_dsp
+    // Use sync. reset for DSP.
+    always_ff @(posedge clk_i) begin
+      if (!rst_ni) begin
+        counter_q <= '0;
+      end else begin
+        counter_q <= counter_d;
+      end
+    end
+  end else begin : g_cnt_no_dsp
+    // Use async. reset for flop.
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+        counter_q <= '0;
+      end else begin
+        counter_q <= counter_d;
+      end
     end
   end
 
+
   if (CounterWidth < 64) begin : g_counter_narrow
     logic [63:CounterWidth] unused_counter_load;
 
@@ -98,6 +109,3 @@ module ibex_counter #(
   assign counter_val_o = counter;
 
 endmodule
-
-// Keep helper defines file-local.
-`undef COUNTER_FLOP_RST