[RV_DM]rv_dm_mem_tl_access_resuming_vseq

Verify that writing to RESUMING results in anyresumeack and allresumeack to be set.When resumereq bit is set, it will clear the anyresumeack and allresumeack.This commit contain some changes like set & clear of haltreq bit and modify comment lines as well.

Signed-off-by: Basit Mehmood <[email protected]>

hw/ip/rv_dm/dv/env/seq_lib/rv_dm_mem_tl_access_resuming_vseq.sv

@@ -19,13 +19,17 @@ class rv_dm_mem_tl_access_resuming_vseq extends rv_dm_base_vseq;
     uvm_reg_data_t wdata;
     uvm_reg_data_t rdata;
     repeat ($urandom_range(1, 10)) begin
-      wdata = $urandom_range(0, 1);
-      // Verify that writing to RESUMING results in anyresumeack and allresumeack to be set,
-      //when resumereq bit is set it will clear the anyresumeack and allresumeack.
+      wdata = $urandom_range(0,1);
+      // Verify that writing to RESUMING results in anyresumeack and
+      // allresumeack to be set.When resumereq bit is set,
+      // it will clear the anyresumeack and allresumeack.
+      csr_wr(.ptr(jtag_dmi_ral.dmcontrol.haltreq), .value(1));
       csr_wr(.ptr(tl_mem_ral.halted), .value(0));
       csr_rd(.ptr(jtag_dmi_ral.dmstatus), .value(rdata));
+      `DV_CHECK_EQ(1, get_field_val(jtag_dmi_ral.dmstatus.anyhalted, rdata))
       `DV_CHECK_EQ(1, get_field_val(jtag_dmi_ral.dmstatus.allhalted, rdata))
       cfg.clk_rst_vif.wait_clks($urandom_range(0, 1000));
+      csr_wr(.ptr(jtag_dmi_ral.dmcontrol.haltreq), .value(0));
       csr_wr(.ptr(tl_mem_ral.resuming), .value(0));
       cfg.clk_rst_vif.wait_clks($urandom_range(0, 1000));
       csr_wr(.ptr(jtag_dmi_ral.dmcontrol.resumereq), .value(wdata));