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[topgen] Improve support for multiple address spaces
Individually generate C and Rust collateral for all address spaces Signed-off-by: Robert Schilling <[email protected]>
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46 changes: 46 additions & 0 deletions
46
hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_dbg_pkg.sv
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// Copyright lowRISC contributors. | ||
// Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
// SPDX-License-Identifier: Apache-2.0 | ||
// | ||
// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// | ||
// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: | ||
// | ||
// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \ | ||
// -o hw/top_darjeeling/ \ | ||
// --rnd_cnst_seed \ | ||
// 1017106219537032642877583828875051302543807092889754935647094601236425074047 | ||
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package top_darjeeling_soc_dbg_pkg; | ||
/** | ||
* Peripheral base address for dmi device on lc_ctrl in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR = 32'h20000; | ||
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/** | ||
* Peripheral size in bytes for dmi device on lc_ctrl in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES = 32'h1000; | ||
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/** | ||
* Peripheral base address for dbg device on rv_dm in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_RV_DM_DBG_BASE_ADDR = 32'h0; | ||
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/** | ||
* Peripheral size in bytes for dbg device on rv_dm in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES = 32'h200; | ||
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/** | ||
* Peripheral base address for soc device on mbx_jtag in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR = 32'h1000; | ||
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/** | ||
* Peripheral size in bytes for soc device on mbx_jtag in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES = 32'h20; | ||
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endpackage |
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106
hw/top_darjeeling/rtl/autogen/top_darjeeling_soc_mbx_pkg.sv
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// Copyright lowRISC contributors. | ||
// Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
// SPDX-License-Identifier: Apache-2.0 | ||
// | ||
// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// | ||
// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: | ||
// | ||
// util/topgen.py -t hw/top_darjeeling/data/top_darjeeling.hjson \ | ||
// -o hw/top_darjeeling/ \ | ||
// --rnd_cnst_seed \ | ||
// 1017106219537032642877583828875051302543807092889754935647094601236425074047 | ||
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package top_darjeeling_soc_mbx_pkg; | ||
/** | ||
* Peripheral base address for soc device on mbx0 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX0_SOC_BASE_ADDR = 32'h1465000; | ||
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/** | ||
* Peripheral size in bytes for soc device on mbx0 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX0_SOC_SIZE_BYTES = 32'h20; | ||
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/** | ||
* Peripheral base address for soc device on mbx1 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX1_SOC_BASE_ADDR = 32'h1465100; | ||
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/** | ||
* Peripheral size in bytes for soc device on mbx1 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX1_SOC_SIZE_BYTES = 32'h20; | ||
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/** | ||
* Peripheral base address for soc device on mbx2 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX2_SOC_BASE_ADDR = 32'h1465200; | ||
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/** | ||
* Peripheral size in bytes for soc device on mbx2 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX2_SOC_SIZE_BYTES = 32'h20; | ||
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/** | ||
* Peripheral base address for soc device on mbx3 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX3_SOC_BASE_ADDR = 32'h1465300; | ||
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/** | ||
* Peripheral size in bytes for soc device on mbx3 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX3_SOC_SIZE_BYTES = 32'h20; | ||
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/** | ||
* Peripheral base address for soc device on mbx4 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX4_SOC_BASE_ADDR = 32'h1465400; | ||
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/** | ||
* Peripheral size in bytes for soc device on mbx4 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX4_SOC_SIZE_BYTES = 32'h20; | ||
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/** | ||
* Peripheral base address for soc device on mbx5 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX5_SOC_BASE_ADDR = 32'h1465500; | ||
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/** | ||
* Peripheral size in bytes for soc device on mbx5 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX5_SOC_SIZE_BYTES = 32'h20; | ||
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/** | ||
* Peripheral base address for soc device on mbx6 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX6_SOC_BASE_ADDR = 32'h1465600; | ||
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/** | ||
* Peripheral size in bytes for soc device on mbx6 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX6_SOC_SIZE_BYTES = 32'h20; | ||
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/** | ||
* Peripheral base address for soc device on mbx_pcie0 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_BASE_ADDR = 32'h1460100; | ||
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/** | ||
* Peripheral size in bytes for soc device on mbx_pcie0 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX_PCIE0_SOC_SIZE_BYTES = 32'h20; | ||
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/** | ||
* Peripheral base address for soc device on mbx_pcie1 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_BASE_ADDR = 32'h1460200; | ||
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/** | ||
* Peripheral size in bytes for soc device on mbx_pcie1 in top darjeeling. | ||
*/ | ||
parameter int unsigned TOP_DARJEELING_MBX_PCIE1_SOC_SIZE_BYTES = 32'h20; | ||
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endpackage |
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70 changes: 70 additions & 0 deletions
70
hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg.rs
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// Copyright lowRISC contributors. | ||
// Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
// SPDX-License-Identifier: Apache-2.0 | ||
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// This file was generated automatically. | ||
// Please do not modify content of this file directly. | ||
// File generated by using template: "toplevel.rs.tpl" | ||
// To regenerate this file follow OpenTitan topgen documentations. | ||
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#![allow(dead_code)] | ||
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//! This file contains enums and consts for use within the Rust codebase. | ||
//! | ||
//! These definitions are for information that depends on the top-specific chip | ||
//! configuration, which includes: | ||
//! - Device Memory Information (for Peripherals and Memory) | ||
//! - PLIC Interrupt ID Names and Source Mappings | ||
//! - Alert ID Names and Source Mappings | ||
//! - Pinmux Pin/Select Names | ||
//! - Power Manager Wakeups | ||
use core::convert::TryFrom; | ||
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/// Peripheral base address for dmi device on lc_ctrl in top darjeeling. | ||
/// | ||
/// This should be used with #mmio_region_from_addr to access the memory-mapped | ||
/// registers associated with the peripheral (usually via a DIF). | ||
pub const TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR: usize = 0x20000; | ||
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/// Peripheral size for dmi device on lc_ctrl in top darjeeling. | ||
/// | ||
/// This is the size (in bytes) of the peripheral's reserved memory area. All | ||
/// memory-mapped registers associated with this peripheral should have an | ||
/// address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and | ||
/// `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`. | ||
pub const TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES: usize = 0x1000; | ||
/// Peripheral base address for dbg device on rv_dm in top darjeeling. | ||
/// | ||
/// This should be used with #mmio_region_from_addr to access the memory-mapped | ||
/// registers associated with the peripheral (usually via a DIF). | ||
pub const TOP_DARJEELING_RV_DM_DBG_BASE_ADDR: usize = 0x0; | ||
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/// Peripheral size for dbg device on rv_dm in top darjeeling. | ||
/// | ||
/// This is the size (in bytes) of the peripheral's reserved memory area. All | ||
/// memory-mapped registers associated with this peripheral should have an | ||
/// address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and | ||
/// `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`. | ||
pub const TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES: usize = 0x200; | ||
/// Peripheral base address for soc device on mbx_jtag in top darjeeling. | ||
/// | ||
/// This should be used with #mmio_region_from_addr to access the memory-mapped | ||
/// registers associated with the peripheral (usually via a DIF). | ||
pub const TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR: usize = 0x1000; | ||
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/// Peripheral size for soc device on mbx_jtag in top darjeeling. | ||
/// | ||
/// This is the size (in bytes) of the peripheral's reserved memory area. All | ||
/// memory-mapped registers associated with this peripheral should have an | ||
/// address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and | ||
/// `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`. | ||
pub const TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES: usize = 0x20; | ||
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/// MMIO Region | ||
/// | ||
/// MMIO region excludes any memory that is separate from the module | ||
/// configuration space, i.e. ROM, main SRAM, and flash are excluded but | ||
/// retention SRAM, spi_device memory, or usbdev memory are included. | ||
pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x1000; | ||
pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0x20000; |
62 changes: 62 additions & 0 deletions
62
hw/top_darjeeling/sw/autogen/chip/top_darjeeling_soc_dbg_memory.rs
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@@ -0,0 +1,62 @@ | ||
// Copyright lowRISC contributors. | ||
// Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
// SPDX-License-Identifier: Apache-2.0 | ||
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// This file was generated automatically. | ||
// Please do not modify content of this file directly. | ||
// File generated by using template: "toplevel_memory.rs.tpl" | ||
// To regenerate this file follow OpenTitan topgen documentations. | ||
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#![allow(dead_code)] | ||
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//! Rust Top-Specific Definitions. | ||
//! | ||
//! This file contains const definitions for use within Rust code. | ||
/// Peripheral base address for dmi device on lc_ctrl in top darjeeling. | ||
/// | ||
/// This should be used with #mmio_region_from_addr to access the memory-mapped | ||
/// registers associated with the peripheral (usually via a DIF). | ||
pub const TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR: usize = 0x20000; | ||
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/// Peripheral size for dmi device on lc_ctrl in top darjeeling. | ||
/// | ||
/// This is the size (in bytes) of the peripheral's reserved memory area. All | ||
/// memory-mapped registers associated with this peripheral should have an | ||
/// address between #TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR and | ||
/// `TOP_DARJEELING_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES`. | ||
pub const TOP_DARJEELING_LC_CTRL_DMI_SIZE_BYTES: usize = 0x1000; | ||
/// Peripheral base address for dbg device on rv_dm in top darjeeling. | ||
/// | ||
/// This should be used with #mmio_region_from_addr to access the memory-mapped | ||
/// registers associated with the peripheral (usually via a DIF). | ||
pub const TOP_DARJEELING_RV_DM_DBG_BASE_ADDR: usize = 0x0; | ||
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/// Peripheral size for dbg device on rv_dm in top darjeeling. | ||
/// | ||
/// This is the size (in bytes) of the peripheral's reserved memory area. All | ||
/// memory-mapped registers associated with this peripheral should have an | ||
/// address between #TOP_DARJEELING_RV_DM_DBG_BASE_ADDR and | ||
/// `TOP_DARJEELING_RV_DM_DBG_BASE_ADDR + TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES`. | ||
pub const TOP_DARJEELING_RV_DM_DBG_SIZE_BYTES: usize = 0x200; | ||
/// Peripheral base address for soc device on mbx_jtag in top darjeeling. | ||
/// | ||
/// This should be used with #mmio_region_from_addr to access the memory-mapped | ||
/// registers associated with the peripheral (usually via a DIF). | ||
pub const TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR: usize = 0x1000; | ||
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/// Peripheral size for soc device on mbx_jtag in top darjeeling. | ||
/// | ||
/// This is the size (in bytes) of the peripheral's reserved memory area. All | ||
/// memory-mapped registers associated with this peripheral should have an | ||
/// address between #TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR and | ||
/// `TOP_DARJEELING_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES`. | ||
pub const TOP_DARJEELING_MBX_JTAG_SOC_SIZE_BYTES: usize = 0x20; | ||
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/// MMIO Region | ||
/// | ||
/// MMIO region excludes any memory that is separate from the module | ||
/// configuration space, i.e. ROM, main SRAM, and flash are excluded but | ||
/// retention SRAM, spi_device memory, or usbdev memory are included. | ||
pub const TOP_DARJEELING_MMIO_BASE_ADDR: usize = 0x1000; | ||
pub const TOP_DARJEELING_MMIO_SIZE_BYTES: usize = 0x20000; |
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