[ipgen,spi_host] Generate 1 or more spi_host (same type) via ipgen

Signed-off-by: Robert Schilling <[email protected]>

hw/ip_templates/BUILD

@@ -12,5 +12,6 @@ filegroup(
         "//hw/ip_templates/pinmux:all_files",
         "//hw/ip_templates/pwrmgr:all_files",
         "//hw/ip_templates/rstmgr:all_files",
+        "//hw/ip_templates/spi_host:all_files",
     ],
 )

hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson

@@ -2187,6 +2187,7 @@
           domain: "0"
         }
       }
+      attr: ipgen
       clock_connections:
       {
         clk_i: clkmgr_aon_clocks.clk_io_div4_peri

hw/top_darjeeling/data/top_darjeeling.hjson

@@ -365,6 +365,7 @@
       base_addr: {
         hart: "0x30300000",
       },
+      attr: "ipgen",
     },
     { name: "pwrmgr_aon",
       type: "pwrmgr",

hw/top_darjeeling/ip_autogen/spi_host/BUILD

@@ -0,0 +1,30 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+load(
+    "//rules:autogen.bzl",
+    "autogen_hjson_c_header",
+    "autogen_hjson_rust_header",
+)
+
+autogen_hjson_c_header(
+    name = "spi_host_c_regs",
+    srcs = [
+        "data/spi_host.hjson",
+    ],
+)
+
+autogen_hjson_rust_header(
+    name = "spi_host_rust_regs",
+    srcs = [
+        "data/spi_host.hjson",
+    ],
+)
+
+filegroup(
+    name = "all_files",
+    srcs = glob(["**"]),
+)

hw/top_darjeeling/ip_autogen/spi_host/README.md

@@ -0,0 +1,50 @@
+# SPI_HOST HWIP Technical Specification
+
+[`spi_host`](https://reports.opentitan.org/hw/ip/spi_host/dv/latest/report.html):
+![](https://dashboards.lowrisc.org/badges/dv/spi_host/test.svg)
+![](https://dashboards.lowrisc.org/badges/dv/spi_host/passing.svg)
+![](https://dashboards.lowrisc.org/badges/dv/spi_host/functional.svg)
+![](https://dashboards.lowrisc.org/badges/dv/spi_host/code.svg)
+
+# Overview
+
+This document specifies SPI_HOST hardware IP (HWIP) functionality.
+This module conforms to the [Comportable guideline for peripheral functionality.](https://opentitan.org/book/doc/contributing/hw/comportability).
+See that document for integration overview within the broader top-level system.
+
+## Features
+
+- Hardware control for remote devices using the Serial Peripheral Interface (SPI)
+- Primarily designed for serial NOR flash devices such as the [Winbond W25Q01JV](https://www.winbond.com/resource-files/W25Q01JV%20SPI%20RevB%2011132019.pdf)
+- Number of chip select lines controlled by `NumCS` parameter
+- Support for Standard SPI, Dual SPI or Quad SPI commands
+  - Signals SD[0] through SD[3] are intended to connect to lines IO<sub>0</sub> through IO<sub>3</sub> respectively, on the target device.
+  - Signal SD[0] may also be identified as "MOSI" by other SPI Hosts, while SD[1] is commonly referred to as "MISO"
+- RX and TX data held in separate FIFOs
+   - 288 bytes for TX data, 256 bytes for RX data
+   - FIFOs loaded/unloaded via 32-bit TL-UL registers
+   - Support for arbitrary byte-count in each transaction
+   - Parametrizable support for Big- or Little-Endian systems in ordering I/O bytes within 32-bit words.
+- SPI clock rate controlled by separate input clock to core
+   - SPI SCK line typically toggles at 1/2 the core clock frequency
+   - An additional clock rate divider exists to reduce the frequency if needed
+- Support for all SPI polarity and phases (CPOL, CPHA)
+   - Additional support for "Full-cycle" SPI transactions, wherein data can be read a full SPI Clock cycle after the active edge (as opposed to one half cycle as is typical for SPI interfaces)
+- Single Transfer Rate (STR) only (i.e. data received on multiple lines, but only on one clock edge)
+   - *No support* for Dual Transfer Rate (DTR)
+- Pass-through mode for coordination with [SPI_DEVICE IP](../spi_device/README.md)
+- Automatic control of chip select lines
+- Condensed interrupt footprint: Two lines for two distinct interrupt classes: "error" and "spi_event"
+   - Fine-grain interrupt masking supplied by secondary enable registers
+
+## Description
+
+The Serial Peripheral Interface (SPI) is a synchronous serial interface, commonly used for NOR flash devices and off-chip peripherals such as ADCs, DACs, or temperature sensors.
+
+The interface is a *de facto* standard (not a formal one), so there is no definitive reference or established compliance criteria.
+It is therefore important to consult the data sheets for the desired peripheral devices in order to ensure compatibility.
+The OpenTitan SPI_HOST IP is primarily designed for controlling Quad SPI NOR flash devices, such as the [W25Q01JV Serial NOR flash from Winbond](https://www.winbond.com/resource-files/W25Q01JV%20SPI%20RevB%2011132019.pdf) or the [1 Gb M25QL NOR flash from Micron](https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_l_01g_bbb_0.pdf?rev=43d124f03bbf4ef0962435e9ec63a185).
+The implementation however is runtime-configurable to support a wide variety of devices, although the Winbond serial flash device is used as the primary reference for understanding our host requirements.
+
+There are also a number of good references describing legacy host implementations for this protocol, which are useful for understanding some of the general needs for a wider range of target devices.
+For instance, the legacy [SPI Block Guide](https://web.archive.org/web/20150413003534/http://www.ee.nmt.edu/~teare/ee308l/datasheets/S12SPIV3.pdf) from Motorola contains a definitive overview of some of the general requirements for a standard SPI host, notably the definitions of SPI clock phase and polarity (CPOL and CPHA).