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[hw,spi_host,rtl] Remove configopts multi register
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FW needs to set up configopts before starting a transfer

Signed-off-by: Robert Schilling <[email protected]>
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@Razer6 @andreaskurth
Razer6 authored and andreaskurth committed Dec 23, 2024
1 parent c31444b commit 6ee0cf0
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146 changes: 72 additions & 74 deletions hw/ip/spi_host/data/spi_host.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -317,81 +317,79 @@
"excl:CsrAllTests:CsrExclCheck"]

},
{ multireg: { name: "CONFIGOPTS",
desc: '''Configuration options register.
{ name: "CONFIGOPTS",
desc: '''Configuration options register.

Contains options for controlling each peripheral. One register per
cs_n line''',
swaccess: "rw",
hwaccess: "hro",
cname: "configopts",
count: "NumCS",
fields: [
{ bits: "31",
name: "CPOL",
desc: '''The polarity of the sck clock signal. When CPOL is 0,
sck is low when idle, and emits high pulses. When CPOL
is 1, sck is high when idle, and emits a series of low
pulses.'''
resval: "0x0"
},
{ bits: "30",
name: "CPHA",
desc: '''The phase of the sck clock signal relative to the data. When
CPHA = 0, the data changes on the trailing edge of sck
and is typically sampled on the leading edge. Conversely
if CPHA = 1 high, data lines change on the leading edge of
sck and are typically sampled on the trailing edge.
CPHA should be chosen to match the phase of the selected
device. The sampling behavior is modified by the
!!CONFIGOPTS.FULLCYC bit.''',
resval: "0x0"
},
{ bits: "29",
name: "FULLCYC",
desc: '''Full cycle. Modifies the CPHA sampling behaviour to allow
for longer device logic setup times. Rather than sampling the SD
bus a half cycle after shifting out data, the data is sampled
a full cycle after shifting data out. This means that if
CPHA = 0, data is shifted out on the trailing edge, and
sampled a full cycle later. If CPHA = 1, data is shifted and
sampled with the trailing edge, also separated by a
full cycle.''',
resval: 0
},
{ bits: "27:24",
name: "CSNLEAD",
desc: '''CS_N Leading Time. Indicates the number of half sck cycles,
CSNLEAD+1, to leave between the falling edge of cs_n and
the first edge of sck. Setting this register to zero
corresponds to the minimum delay of one-half sck cycle'''
resval: 0
},
{ bits: "23:20",
name: "CSNTRAIL"
desc: '''CS_N Trailing Time. Indicates the number of half sck cycles,
CSNTRAIL+1, to leave between last edge of sck and the rising
edge of cs_n. Setting this register to zero corresponds
to the minimum delay of one-half sck cycle.'''
resval: 0
},
{ bits: "19:16",
name: "CSNIDLE"
desc: '''Minimum idle time between commands. Indicates the minimum
number of sck half-cycles to hold cs_n high between commands.
Setting this register to zero creates a minimally-wide CS_N-high
pulse of one-half sck cycle.'''
resval: 0
},
{ bits: "15:0",
name: "CLKDIV",
desc: '''Core clock divider. Slows down subsequent SPI transactions by a
factor of (CLKDIV+1) relative to the core clock frequency. The
period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)`'''
resval: 0
},
]
}
Contains options for controlling the current peripheral.
Firmware needs to configure the options before the transfer.
'''
swaccess: "rw",
hwaccess: "hro",
fields: [
{ bits: "31",
name: "CPOL",
desc: '''The polarity of the sck clock signal. When CPOL is 0,
sck is low when idle, and emits high pulses. When CPOL
is 1, sck is high when idle, and emits a series of low
pulses.'''
resval: "0x0"
},
{ bits: "30",
name: "CPHA",
desc: '''The phase of the sck clock signal relative to the data. When
CPHA = 0, the data changes on the trailing edge of sck
and is typically sampled on the leading edge. Conversely
if CPHA = 1 high, data lines change on the leading edge of
sck and are typically sampled on the trailing edge.
CPHA should be chosen to match the phase of the selected
device. The sampling behavior is modified by the
!!CONFIGOPTS.FULLCYC bit.''',
resval: "0x0"
},
{ bits: "29",
name: "FULLCYC",
desc: '''Full cycle. Modifies the CPHA sampling behaviour to allow
for longer device logic setup times. Rather than sampling the SD
bus a half cycle after shifting out data, the data is sampled
a full cycle after shifting data out. This means that if
CPHA = 0, data is shifted out on the trailing edge, and
sampled a full cycle later. If CPHA = 1, data is shifted and
sampled with the trailing edge, also separated by a
full cycle.''',
resval: 0
},
{ bits: "27:24",
name: "CSNLEAD",
desc: '''CS_N Leading Time. Indicates the number of half sck cycles,
CSNLEAD+1, to leave between the falling edge of cs_n and
the first edge of sck. Setting this register to zero
corresponds to the minimum delay of one-half sck cycle'''
resval: 0
},
{ bits: "23:20",
name: "CSNTRAIL"
desc: '''CS_N Trailing Time. Indicates the number of half sck cycles,
CSNTRAIL+1, to leave between last edge of sck and the rising
edge of cs_n. Setting this register to zero corresponds
to the minimum delay of one-half sck cycle.'''
resval: 0
},
{ bits: "19:16",
name: "CSNIDLE"
desc: '''Minimum idle time between commands. Indicates the minimum
number of sck half-cycles to hold cs_n high between commands.
Setting this register to zero creates a minimally-wide CS_N-high
pulse of one-half sck cycle.'''
resval: 0
},
{ bits: "15:0",
name: "CLKDIV",
desc: '''Core clock divider. Slows down subsequent SPI transactions by a
factor of (CLKDIV+1) relative to the core clock frequency. The
period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)`'''
resval: 0
},
]
},
{ name: "CSID",
desc: '''Chip-Select ID
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68 changes: 31 additions & 37 deletions hw/ip/spi_host/doc/registers.md
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Original file line number Diff line number Diff line change
Expand Up @@ -171,18 +171,12 @@ Status register
## CONFIGOPTS
Configuration options register.

Contains options for controlling each peripheral. One register per
cs_n line
Contains options for controlling the current peripheral.
Firmware needs to configure the options before the transfer.
- Offset: `0x18`
- Reset default: `0x0`
- Reset mask: `0xefffffff`

### Instances

| Name | Offset |
|:-----------|:---------|
| CONFIGOPTS | 0x18 |


### Fields

```wavejson
Expand All @@ -202,52 +196,52 @@ Configuration options register.

### CONFIGOPTS . CPOL
The polarity of the sck clock signal. When CPOL is 0,
sck is low when idle, and emits high pulses. When CPOL
is 1, sck is high when idle, and emits a series of low
pulses.
sck is low when idle, and emits high pulses. When CPOL
is 1, sck is high when idle, and emits a series of low
pulses.

### CONFIGOPTS . CPHA
The phase of the sck clock signal relative to the data. When
CPHA = 0, the data changes on the trailing edge of sck
and is typically sampled on the leading edge. Conversely
if CPHA = 1 high, data lines change on the leading edge of
sck and are typically sampled on the trailing edge.
CPHA should be chosen to match the phase of the selected
device. The sampling behavior is modified by the
[`CONFIGOPTS.FULLCYC`](#configopts) bit.
CPHA = 0, the data changes on the trailing edge of sck
and is typically sampled on the leading edge. Conversely
if CPHA = 1 high, data lines change on the leading edge of
sck and are typically sampled on the trailing edge.
CPHA should be chosen to match the phase of the selected
device. The sampling behavior is modified by the
[`CONFIGOPTS.FULLCYC`](#configopts) bit.

### CONFIGOPTS . FULLCYC
Full cycle. Modifies the CPHA sampling behaviour to allow
for longer device logic setup times. Rather than sampling the SD
bus a half cycle after shifting out data, the data is sampled
a full cycle after shifting data out. This means that if
CPHA = 0, data is shifted out on the trailing edge, and
sampled a full cycle later. If CPHA = 1, data is shifted and
sampled with the trailing edge, also separated by a
full cycle.
for longer device logic setup times. Rather than sampling the SD
bus a half cycle after shifting out data, the data is sampled
a full cycle after shifting data out. This means that if
CPHA = 0, data is shifted out on the trailing edge, and
sampled a full cycle later. If CPHA = 1, data is shifted and
sampled with the trailing edge, also separated by a
full cycle.

### CONFIGOPTS . CSNLEAD
CS_N Leading Time. Indicates the number of half sck cycles,
CSNLEAD+1, to leave between the falling edge of cs_n and
the first edge of sck. Setting this register to zero
corresponds to the minimum delay of one-half sck cycle
CSNLEAD+1, to leave between the falling edge of cs_n and
the first edge of sck. Setting this register to zero
corresponds to the minimum delay of one-half sck cycle

### CONFIGOPTS . CSNTRAIL
CS_N Trailing Time. Indicates the number of half sck cycles,
CSNTRAIL+1, to leave between last edge of sck and the rising
edge of cs_n. Setting this register to zero corresponds
to the minimum delay of one-half sck cycle.
CSNTRAIL+1, to leave between last edge of sck and the rising
edge of cs_n. Setting this register to zero corresponds
to the minimum delay of one-half sck cycle.

### CONFIGOPTS . CSNIDLE
Minimum idle time between commands. Indicates the minimum
number of sck half-cycles to hold cs_n high between commands.
Setting this register to zero creates a minimally-wide CS_N-high
pulse of one-half sck cycle.
number of sck half-cycles to hold cs_n high between commands.
Setting this register to zero creates a minimally-wide CS_N-high
pulse of one-half sck cycle.

### CONFIGOPTS . CLKDIV
Core clock divider. Slows down subsequent SPI transactions by a
factor of (CLKDIV+1) relative to the core clock frequency. The
period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)`
factor of (CLKDIV+1) relative to the core clock frequency. The
period of sck, T(sck) then becomes `2*(CLK_DIV+1)*T(core)`

## CSID
Chip-Select ID
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14 changes: 7 additions & 7 deletions hw/ip/spi_host/dv/README.md
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Expand Up @@ -74,13 +74,13 @@ All common types and methods defined at the package level can be found in
// spi config
typedef struct {
// configopts register fields
rand bit cpol[SPI_HOST_NUM_CS];
rand bit cpha[SPI_HOST_NUM_CS];
rand bit fullcyc[SPI_HOST_NUM_CS];
rand bit [3:0] csnlead[SPI_HOST_NUM_CS];
rand bit [3:0] csntrail[SPI_HOST_NUM_CS];
rand bit [3:0] csnidle[SPI_HOST_NUM_CS];
rand bit [15:0] clkdiv[SPI_HOST_NUM_CS];
rand bit cpol;
rand bit cpha;
rand bit fullcyc;
rand bit [3:0] csnlead;
rand bit [3:0] csntrail;
rand bit [3:0] csnidle;
rand bit [15:0] clkdiv;
} spi_host_configopts_t;
typedef struct {
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