[hw,dma,rtl] Remove memory threshold interrupt from RTL and DIF

Signed-off-by: Robert Schilling <[email protected]>
lowRISC · Jul 24, 2024 · 6e63cd1 · 6e63cd1
1 parent 0eec3b9
commit 6e63cd1
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Showing 24 changed files with 385 additions and 1,324 deletions.
diff --git a/hw/ip/dma/data/dma.hjson b/hw/ip/dma/data/dma.hjson
@@ -104,9 +104,6 @@
     { name: "dma_error"
       desc: "DMA error has occurred. DMA_STATUS.error_code register shows the details."
     }
-    { name: "dma_memory_buffer_limit"
-      desc: "Memory buffer limit address reached."
-    }
   ]
   alert_list: [
     { name: "fatal_fault"
@@ -423,86 +420,6 @@
         }
       ]
     }
-    { name: "DST_ADDR_LIMIT_LO"
-      desc: "Lower 32 bits of DMA memory buffer limit address."
-      swaccess: "rw"
-      hwaccess: "hro"
-      regwen: "CFG_REGWEN"
-      fields: [
-        { bits: "31:0"
-          name: "addr_limit_lo"
-          resval: 0x0
-          desc: '''
-                Limit address configuration.
-
-                Used in conjunction with the address auto-increment mode for hardware handshake operation to
-                generate an interrupt when memory buffer address approaches memory buffer address limit.
-                This field is optional.
-                However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set.
-                '''
-        }
-      ]
-    }
-    { name: "DST_ADDR_LIMIT_HI"
-      desc: "Upper 32 bits of DMA memory buffer limit address."
-      swaccess: "rw"
-      hwaccess: "hro"
-      regwen: "CFG_REGWEN"
-      fields: [
-        { bits: "31:0"
-          name: "addr_limit_hi"
-          resval: 0x0
-          desc: '''
-                Limit address configuration.
-
-                Used in conjunction with the address auto-increment mode for hardware handshake operation to
-                generate an interrupt when memory buffer address approaches memory buffer address limit.
-                This field is optional.
-                However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set.
-                '''
-        }
-      ]
-    }
-    { name: "DST_ADDR_ALMOST_LIMIT_LO"
-      desc: "Lower 32 bits of DMA memory buffer limit address."
-      swaccess: "rw"
-      hwaccess: "hro"
-      regwen: "CFG_REGWEN"
-      fields: [
-        { bits: "31:0"
-          name: "addr_limit_lo"
-          resval: 0x0
-          desc: '''
-                Threshold for detecting that the buffer limit is approaching so as to prevent destination buffer overflow.
-                Used in conjunction with the address auto-increment mode for hardware handshake operation to generate an
-                interrupt when the buffer address approaches close to the buffer (i.e. reaches this threshold) address limit.
-                Enables firmware to take appropriate action prior to reaching the final limit.
-                This field is optional.
-                However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set.
-                '''
-        }
-      ]
-    }
-    { name: "DST_ADDR_ALMOST_LIMIT_HI"
-      desc: "Upper 32 bits of DMA memory buffer limit address."
-      swaccess: "rw"
-      hwaccess: "hro"
-      regwen: "CFG_REGWEN"
-      fields: [
-        { bits: "31:0"
-          name: "addr_limit_hi"
-          resval: 0x0
-          desc: '''
-                Threshold for detecting that the buffer limit is approaching so as to prevent destination buffer overflow.
-                Used in conjunction with the address auto-increment mode for hardware handshake operation to generate an
-                interrupt when the buffer address approaches close to the buffer (i.e. reaches this threshold) address limit.
-                Enables firmware to take appropriate action prior to reaching the final limit.
-                This field is optional.
-                However this field is expected to be implicitly valid if the CONTROL.memory_buffer_auto_increment_enable register (bit 7) is set.
-                '''
-        }
-      ]
-    }
     { name: "CONTROL"
       desc: "Control register for DMA data movement."
       swaccess: "rw"
@@ -804,7 +721,7 @@
         ]
       }
     }
-    { skipto: "0x12C" }
+    { skipto: "0x11C" }
     { multireg: {
         name: "INTR_SRC_WR_VAL"
         desc: "Write value for interrupt clearing write."

diff --git a/hw/ip/dma/data/dma_testplan.hjson b/hw/ip/dma/data/dma_testplan.hjson
@@ -226,13 +226,9 @@
               Stimulus:
               - Configure DMA for 'hardware handshake' mode
               - Set memory_buffer_addr_auto_increment
-              - Set memory_buffer_threshold and memory_buffer_limit such that
-                * Threshold is less than the limit and
-                * Threshold and limit are within the DMA memory region
               - Start DMA operation by setting DMAC.GO bit
               - Assert Low Speed IO (LSIO) interrupt
               - Wait for TLUL transaction on the output interface
-              - Respond with random number of data items such that the amount exceeds either the memory_buffer_threshold or memory_buffer_limit
               - Deassert LSIO interrupt
               - Wait for the operation to complete
               - Repeat the operation with different source and destination parameters
@@ -245,7 +241,7 @@
               - Check if PLIC interrupt is asserted when memory_buffer_auto_increment is enabled
               '''
         stage: V2
-        tests: ["dma_handshake_stress", "dma_mem_limit"]
+        tests: ["dma_handshake_stress"]
       }
       {
         name: dma_abort
@@ -308,8 +304,6 @@
                  * Total data size
                  * Chunk data size
                  * Transfer width
-                 * Destination address limit
-                 * Destination address almost limit
                  * Control register fields:
                    + opcode
                    + hardware handshake enable
@@ -330,7 +324,7 @@
                  * opcode, hardware handshake enable, data direction, and initial transfer
                  * source and destination address, DMA-enabled memory range base and limit, and data direction
                  * source and destination address alignment, total data size alignment, and transfer width
-                 * memory buffer auto increment enable, data direction, and the results of (destination address + total data size) compared to {destination address limit, destination address almost limit}
+                 * memory buffer auto increment enable, data direction, and the results of (destination address + total data size)
                '''
       }
       {