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[topgen] Generically filter for MMIO region visible devices
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Add a new subspace entry to the address spaces to group multple
address to the same address space. For this subspace, the range
is computed and added as a definition to the C and Rust collateral.

Signed-off-by: Robert Schilling <[email protected]>
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@Razer6
Razer6 committed Jun 5, 2024
1 parent 3216fab commit 6bb9699
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Showing 22 changed files with 465 additions and 163 deletions.
93 changes: 93 additions & 0 deletions hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -454,6 +454,63 @@
{
name: hart
desc: The main address space, shared between the CPU and DM
subspaces:
[
{
name: mmio
desc:
'''
MMIO region excludes any memory that is separate from the module configuration
space, i.e. ROM, main SRAM, and MBX SRAM are excluded but retention SRAM or
spi_device are included.
'''
nodes:
[
uart0
gpio
spi_device
i2c0
rv_timer
otp_ctrl
lc_ctrl.regs
alert_handler
spi_host0
pwrmgr_aon
rstmgr_aon
clkmgr_aon
pinmux_aon
aon_timer_aon
sensor_ctrl
soc_proxy.core
sram_ctrl_ret_aon
rv_dm.regs
rv_plic
aes
hmac
otbn
keymgr_dpe
csrng
edn0
edn1
sram_ctrl_main.regs
sram_ctrl_mbox.regs
rom_ctrl0.regs
rom_ctrl1.regs
dma
mbx0.core
mbx1.core
mbx2.core
mbx3.core
mbx4.core
mbx5.core
mbx6.core
mbx_jtag.core
mbx_pcie0.core
mbx_pcie1.core
rv_core_ibex
]
}
]
}
{
name: soc_mbx
Expand Down Expand Up @@ -3750,6 +3807,7 @@
ctn:
{
hart: 0x40000000
cpu_visible: false
}
}
attr: reggen_top
Expand Down Expand Up @@ -4267,14 +4325,17 @@
mem:
{
hart: 0x00040000
cpu_visible: false
}
regs:
{
hart: 0x21200000
cpu_visible: false
}
dbg:
{
soc_dbg: 0x00000000
cpu_visible: false
}
}
param_decl:
Expand Down Expand Up @@ -6092,6 +6153,7 @@
ram:
{
hart: 0x10000000
cpu_visible: false
}
}
memory:
Expand Down Expand Up @@ -6299,6 +6361,7 @@
ram:
{
hart: 0x11000000
cpu_visible: false
}
}
memory:
Expand Down Expand Up @@ -6490,6 +6553,7 @@
rom:
{
hart: 0x00008000
cpu_visible: false
}
regs:
{
Expand Down Expand Up @@ -6672,6 +6736,7 @@
rom:
{
hart: 0x00020000
cpu_visible: false
}
regs:
{
Expand Down Expand Up @@ -7022,6 +7087,7 @@
soc:
{
soc_mbx: 0x01465000
cpu_visible: false
}
}
clock_connections:
Expand Down Expand Up @@ -7158,6 +7224,7 @@
soc:
{
soc_mbx: 0x01465100
cpu_visible: false
}
}
clock_connections:
Expand Down Expand Up @@ -7294,6 +7361,7 @@
soc:
{
soc_mbx: 0x01465200
cpu_visible: false
}
}
clock_connections:
Expand Down Expand Up @@ -7430,6 +7498,7 @@
soc:
{
soc_mbx: 0x01465300
cpu_visible: false
}
}
clock_connections:
Expand Down Expand Up @@ -7566,6 +7635,7 @@
soc:
{
soc_mbx: 0x01465400
cpu_visible: false
}
}
clock_connections:
Expand Down Expand Up @@ -7702,6 +7772,7 @@
soc:
{
soc_mbx: 0x01465500
cpu_visible: false
}
}
clock_connections:
Expand Down Expand Up @@ -7838,6 +7909,7 @@
soc:
{
soc_mbx: 0x01465600
cpu_visible: false
}
}
clock_connections:
Expand Down Expand Up @@ -7974,6 +8046,7 @@
soc:
{
soc_dbg: 0x1000
cpu_visible: false
}
}
clock_connections:
Expand Down Expand Up @@ -8110,6 +8183,7 @@
soc:
{
soc_mbx: 0x01460100
cpu_visible: false
}
}
clock_connections:
Expand Down Expand Up @@ -8246,6 +8320,7 @@
soc:
{
soc_mbx: 0x01460200
cpu_visible: false
}
}
clock_connections:
Expand Down Expand Up @@ -9990,6 +10065,7 @@
base_addrs:
{
hart: 0x21200000
cpu_visible: 0x0
}
size_byte: 0x4
}
Expand All @@ -10012,6 +10088,7 @@
base_addrs:
{
hart: 0x40000
cpu_visible: 0x0
}
size_byte: 0x1000
}
Expand All @@ -10034,6 +10111,7 @@
base_addrs:
{
hart: 0x8000
cpu_visible: 0x0
}
size_byte: 0x8000
}
Expand Down Expand Up @@ -10078,6 +10156,7 @@
base_addrs:
{
hart: 0x20000
cpu_visible: 0x0
}
size_byte: 0x10000
}
Expand Down Expand Up @@ -10165,6 +10244,7 @@
base_addrs:
{
hart: 0x40000000
cpu_visible: 0x0
}
size_byte: 0x40000000
}
Expand Down Expand Up @@ -10429,6 +10509,7 @@
base_addrs:
{
hart: 0x10000000
cpu_visible: 0x0
}
size_byte: 0x10000
}
Expand Down Expand Up @@ -10471,6 +10552,7 @@
base_addrs:
{
hart: 0x11000000
cpu_visible: 0x0
}
size_byte: 0x1000
}
Expand Down Expand Up @@ -12250,6 +12332,7 @@
base_addrs:
{
soc_mbx: 0x1465000
cpu_visible: 0x0
}
size_byte: 0x20
}
Expand All @@ -12272,6 +12355,7 @@
base_addrs:
{
soc_mbx: 0x1465100
cpu_visible: 0x0
}
size_byte: 0x20
}
Expand All @@ -12294,6 +12378,7 @@
base_addrs:
{
soc_mbx: 0x1465200
cpu_visible: 0x0
}
size_byte: 0x20
}
Expand All @@ -12316,6 +12401,7 @@
base_addrs:
{
soc_mbx: 0x1465300
cpu_visible: 0x0
}
size_byte: 0x20
}
Expand All @@ -12338,6 +12424,7 @@
base_addrs:
{
soc_mbx: 0x1465400
cpu_visible: 0x0
}
size_byte: 0x20
}
Expand All @@ -12360,6 +12447,7 @@
base_addrs:
{
soc_mbx: 0x1465500
cpu_visible: 0x0
}
size_byte: 0x20
}
Expand All @@ -12382,6 +12470,7 @@
base_addrs:
{
soc_mbx: 0x1465600
cpu_visible: 0x0
}
size_byte: 0x20
}
Expand All @@ -12404,6 +12493,7 @@
base_addrs:
{
soc_mbx: 0x1460100
cpu_visible: 0x0
}
size_byte: 0x20
}
Expand All @@ -12426,6 +12516,7 @@
base_addrs:
{
soc_mbx: 0x1460200
cpu_visible: 0x0
}
size_byte: 0x20
}
Expand Down Expand Up @@ -12635,6 +12726,7 @@
base_addrs:
{
soc_dbg: 0x0
cpu_visible: 0x0
}
size_byte: 0x200
}
Expand All @@ -12656,6 +12748,7 @@
base_addrs:
{
soc_dbg: 0x1000
cpu_visible: 0x0
}
size_byte: 0x20
}
Expand Down
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