[tools,otp_images] Move the tools to generate otp images

- Most of the OTP image generation tools are top-specific so they are moved to hw/top_earlgrey/data/otp. The few things that are generic move to util/design/data. - Adjust paths to targets that moved. - Merge hw/ip/otp_ctrl/data/README.md into util/design/README.md. - Adjust some paths to README.md files. - Change the path to the otp_ctrl_mmap.hjson in get-otp-mmap.py. Part of #25019 Signed-off-by: Guillermo Maturana <[email protected]>
lowRISC · Dec 4, 2024 · 6bb76fc · 6bb76fc
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diff --git a/BLOCKFILE b/BLOCKFILE
@@ -92,19 +92,19 @@ hw/ip/otbn/data/otbn.hjson
 hw/ip/entropy_src/data/entropy_src.hjson
 hw/ip/aes/data/aes.hjson
 hw/ip/i2c/data/i2c.hjson
-hw/ip/otp_ctrl/data/otp_ctrl.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_img_rma.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_img_dev.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_img_test_locked0.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_img_test_locked1.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_img_test_unlocked0.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_img_creator_sw_cfg.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_img_hw_cfg.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_img_raw.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_mmap.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_img_test_unlocked1.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_img_prod.hjson
-hw/ip/otp_ctrl/data/otp_ctrl_img_test_unlocked2.hjson
+hw/top_earlgrey/data/otp/otp_ctrl.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_img_rma.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_img_dev.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_img_test_locked0.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_img_test_locked1.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_img_test_unlocked0.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_img_creator_sw_cfg.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_img_hw_cfg.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_img_raw.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_img_test_unlocked1.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_img_prod.hjson
+hw/top_earlgrey/data/otp/otp_ctrl_img_test_unlocked2.hjson
 hw/ip/rv_core_ibex/data/rv_core_ibex.hjson
 hw/ip/pwm/data/pwm.hjson
 hw/ip/aon_timer/data/aon_timer.hjson

diff --git a/SUMMARY.md b/SUMMARY.md
@@ -417,7 +417,7 @@
 - [Device Software](./sw/device/README.md)
   - [Build & Test Rules](./rules/opentitan/README.md)
     - [FPGA Bitstreams](./hw/bitstream/README.md)
-    - [OTP Build and Test Infrastructure](./hw/ip/otp_ctrl/data/README.md)
+    - [OTP Preload Image Generator](./util/design/README.md#otp_preload_image_generator)
   - [Device Libraries](./sw/device/lib/README.md)
     - [DIF Library](./sw/device/lib/dif/README.md)
       - [ADC Checklist](sw/device/lib/dif/dif_adc_ctrl.md)

diff --git a/ci/scripts/run-english-breakfast-verilator-tests.sh b/ci/scripts/run-english-breakfast-verilator-tests.sh
@@ -21,7 +21,7 @@ ci/bazelisk.sh clean
 ci/bazelisk.sh build  \
     --copt=-DOT_IS_ENGLISH_BREAKFAST_REDUCED_SUPPORT_FOR_INTERNAL_USE_ONLY_ \
     --features=-rv32_bitmanip \
-    //sw/host/opentitantool //hw/ip/otp_ctrl/data:img_rma
+    //sw/host/opentitantool //hw/top_earlgrey/data/otp:img_rma
 
 # Run the one test.
 # This needs to be run outside the bazel sandbox, so we do not use `bazel run`

diff --git a/doc/getting_started/setup_fpga.md b/doc/getting_started/setup_fpga.md
@@ -69,7 +69,7 @@ Specifically, you can build the [`//hw/bitstream/universal:splice`](https://gith
 For example, to splice a CW310 bitstream with the mask ROM image and a specific OTP image, you can run
 ```sh
 bazel build \
-    --//hw/bitstream/universal:otp=//hw/ip/otp_ctrl/data:img_dev \
+    --//hw/bitstream/universal:otp=//hw/top_earlgrey/data/otp:img_dev \
     --//hw/bitstream/universal:env=//hw/top_earlgrey:fpga_cw310_rom_with_fake_keys \
     //hw/bitstream/universal:splice
 ```

diff --git a/doc/getting_started/setup_verilator.md b/doc/getting_started/setup_verilator.md
@@ -74,8 +74,8 @@ bazel test --test_tag_filters=verilator --test_output=streamed //sw/device/tests
 
 You should expect to see something like:
 ```console
-Invoking: sw/host/opentitantool/opentitantool --rcfile= --logging=info --interface=verilator --verilator-bin=hw/build.verilator_real/sim-verilator/Vchip_sim_tb --verilator-rom=sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem --verilator-flash=sw/device/tests/uart_smoketest_prog_sim_verilator.64.scr.vmem --verilator-otp=hw/ip/otp_ctrl/data/img_rma.vmem console --exit-failure=(FAIL|FAULT).*\n --exit-success=PASS.*\n --timeout=3600s
-[2022-06-09T08:08:16Z INFO  opentitanlib::transport::verilator::subprocess] Spawning verilator: "hw/build.verilator_real/sim-verilator/Vchip_sim_tb" ["--meminit=rom,sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem", "--meminit=flash,sw/device/tests/uart_smoketest_prog_sim_verilator.64.scr.vmem", "--meminit=otp,hw/ip/otp_ctrl/data/img_rma.vmem"]
+Invoking: sw/host/opentitantool/opentitantool --rcfile= --logging=info --interface=verilator --verilator-bin=hw/build.verilator_real/sim-verilator/Vchip_sim_tb --verilator-rom=sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem --verilator-flash=sw/device/tests/uart_smoketest_prog_sim_verilator.64.scr.vmem --verilator-otp=hw/top_earlgrey/data/otp/img_rma.vmem console --exit-failure=(FAIL|FAULT).*\n --exit-success=PASS.*\n --timeout=3600s
+[2022-06-09T08:08:16Z INFO  opentitanlib::transport::verilator::subprocess] Spawning verilator: "hw/build.verilator_real/sim-verilator/Vchip_sim_tb" ["--meminit=rom,sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem", "--meminit=flash,sw/device/tests/uart_smoketest_prog_sim_verilator.64.scr.vmem", "--meminit=otp,hw/top_earlgrey/data/otp/img_rma.vmem"]
 [2022-06-09T08:08:16Z INFO  opentitanlib::transport::verilator::stdout] Simulation of OpenTitan Earl Grey
 [2022-06-09T08:08:16Z INFO  opentitanlib::transport::verilator::stdout] =================================
 [2022-06-09T08:08:16Z INFO  opentitanlib::transport::verilator::stdout]

diff --git a/hw/bitstream/README.md b/hw/bitstream/README.md
@@ -35,7 +35,7 @@ opentitan_test(
     name = "individualize_sw_cfg_functest",
     srcs = ["individualize_sw_cfg_functest.c"],
     fpga = fpga_params(
-        otp = "//hw/ip/otp_ctrl/data/earlgrey_skus/sival:otp_img_test_unlocked0_manuf_initialized",
+        otp = "//hw/top_earlgrey/data/otp/sival_skus:otp_img_test_unlocked0_manuf_initialized",
         tags = ["manuf"],
     ),
     exec_env = {
@@ -98,4 +98,4 @@ opentitan_test(
 
 ## Read More
 
-* [OTP Build and Test Infrastructure](../ip/otp_ctrl/data/README.md)
+* [OTP Preload Image Generator](../../util/design/README.md#otp_preload_image_generator)
diff --git a/hw/bitstream/vivado/BUILD b/hw/bitstream/vivado/BUILD
@@ -24,7 +24,7 @@ _CW310_TESTROM = "//sw/device/lib/testing/test_rom:test_rom_fpga_cw310_scr_vmem"
 
 _CW340_TESTROM = _CW310_TESTROM
 
-_OTP_RMA = "//hw/ip/otp_ctrl/data:img_rma"
+_OTP_RMA = "//hw/top_earlgrey/data/otp:img_rma"
 
 _CW310_TESTROM_PATH = "{}/$(location {})".format(_PREFIX, _CW310_TESTROM)
 

diff --git a/hw/dv/tools/dvsim/sim.mk b/hw/dv/tools/dvsim/sim.mk
@@ -101,13 +101,13 @@ ifneq (${sw_images},)
 			echo "Building SW image \"$${bazel_label}\"."; \
 			bazel_airgapped_opts=""; \
 			bazel_opts="${sw_build_opts} --define DISABLE_VERILATOR_BUILD=true"; \
-			bazel_opts+=" --//hw/ip/otp_ctrl/data:img_seed=${seed}"; \
+			bazel_opts+=" --//util/design/data:img_seed=${seed}"; \
 			if [[ "${build_seed}" != "None" ]]; then \
-				bazel_opts+=" --//hw/ip/otp_ctrl/data:lc_seed=${build_seed}"; \
-				bazel_opts+=" --//hw/ip/otp_ctrl/data:otp_seed=${build_seed}"; \
+				bazel_opts+=" --//util/design/data:lc_seed=${build_seed}"; \
+				bazel_opts+=" --//util/design/data:otp_seed=${build_seed}"; \
 			fi; \
 			if [[ -n $${BAZEL_OTP_DATA_PERM_FLAG} ]]; then \
-				bazel_opts+=" --//hw/ip/otp_ctrl/data:data_perm=$${BAZEL_OTP_DATA_PERM_FLAG}"; \
+				bazel_opts+=" --//util/design/data:data_perm=$${BAZEL_OTP_DATA_PERM_FLAG}"; \
 			fi; \
 			if [[ $${OT_AIRGAPPED} != true ]]; then \
 				echo "Building \"$${bazel_label}\" on network connected machine."; \