[aes, kmac, otbn] Perform final clean -purge step in Yosys synthesis

The `-purge` argument will remove dangling wires in the final netlist introduced due to the keep[_hierarchy] constraints and the flattening step after removing these constraints. Removing these wires reduces the size of netlist considerably thereby speeding up analysis using tools like PROLEAD. Signed-off-by: Pirmin Vogel <[email protected]>
lowRISC · May 7, 2024 · 3ef84c5 · 3ef84c5
1 parent 954fbad
commit 3ef84c5
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Showing 3 changed files with 3 additions and 5 deletions.
diff --git a/hw/ip/aes/pre_syn/tcl/yosys_run_synth.tcl b/hw/ip/aes/pre_syn/tcl/yosys_run_synth.tcl
@@ -81,7 +81,7 @@ if { $lr_synth_flatten } {
   yosys "flatten"
 }
 
-yosys "clean"
+yosys "clean -purge"
 yosys "write_verilog $lr_synth_netlist_out"
 
 if { $lr_synth_timing_run } {
@@ -96,4 +96,3 @@ yosys "check"
 yosys "log ======== Yosys Stat Report ========"
 yosys "tee -o $lr_synth_out_dir/reports/area.rpt stat -liberty $lr_synth_cell_library_path"
 yosys "log ====== End Yosys Stat Report ======"
-
diff --git a/hw/ip/kmac/pre_syn/tcl/yosys_run_synth.tcl b/hw/ip/kmac/pre_syn/tcl/yosys_run_synth.tcl
@@ -64,7 +64,7 @@ if { $lr_synth_flatten } {
   yosys "flatten"
 }
 
-yosys "clean"
+yosys "clean -purge"
 yosys "write_verilog $lr_synth_netlist_out"
 
 if { $lr_synth_timing_run } {
@@ -79,4 +79,3 @@ yosys "check"
 yosys "log ======== Yosys Stat Report ========"
 yosys "tee -o $lr_synth_out_dir/reports/area.rpt stat -liberty $lr_synth_cell_library_path"
 yosys "log ====== End Yosys Stat Report ======"
-
diff --git a/hw/ip/otbn/pre_syn/tcl/yosys_run_synth.tcl b/hw/ip/otbn/pre_syn/tcl/yosys_run_synth.tcl
@@ -64,7 +64,7 @@ if { $lr_synth_flatten } {
   yosys "flatten"
 }
 
-yosys "clean"
+yosys "clean -purge"
 yosys "write_verilog $lr_synth_netlist_out"
 
 if { $lr_synth_timing_run } {