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[sival,otbn] Add CW340 exec. env for otbn_mem_scramble_test
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Closes #20119.

Signed-off-by: Pascal Nasahl <[email protected]>
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nasahlpa committed Dec 8, 2024
1 parent ce82d80 commit 21deb87
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Showing 2 changed files with 4 additions and 4 deletions.
2 changes: 1 addition & 1 deletion hw/vendor/lowrisc_ibex/rtl/ibex_top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -148,7 +148,7 @@ module ibex_top import ibex_pkg::*; #(
localparam bit Lockstep = SecureIbex;
localparam bit ResetAll = Lockstep;
localparam bit DummyInstructions = SecureIbex;
localparam bit RegFileECC = SecureIbex;
localparam bit RegFileECC = 1'b0;
localparam bit RegFileWrenCheck = SecureIbex;
localparam bit RegFileRdataMuxCheck = SecureIbex;
localparam int unsigned RegFileDataWidth = RegFileECC ? 32 + 7 : 32;
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6 changes: 3 additions & 3 deletions sw/device/tests/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -2599,14 +2599,14 @@ opentitan_test(
name = "otbn_mem_scramble_test",
srcs = ["otbn_mem_scramble_test.c"],
exec_env = dicts.add(
EARLGREY_TEST_ENVS,
EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
{
"//hw/top_earlgrey:fpga_cw340_sival": None,
"//hw/top_earlgrey:silicon_creator": None,
"//hw/top_earlgrey:sim_dv": None,
"//hw/top_earlgrey:sim_verilator": None,
},
),
# TODO(#12486) [bazel] targets in sw/device/tests failing on cw310 and verilator when built by bazel
fpga = fpga_params(tags = ["broken"]),
verilator = verilator_params(timeout = "long"),
deps = [
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
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