Skip to content

Commit

Permalink
[dv, rstmgr] Increate dvsim timeout for alert_info test
Browse files Browse the repository at this point in the history
Signed-off-by: Douglas Reis <[email protected]>
  • Loading branch information
engdoreis committed May 2, 2024
1 parent 32d2c5c commit 2123499
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion hw/top_earlgrey/dv/chip_sim_cfg.hjson
Original file line number Diff line number Diff line change
Expand Up @@ -971,7 +971,7 @@
uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests:rstmgr_alert_info_test:1:new_rules"]
en_run_modes: ["sw_test_mode_test_rom"]
run_opts: ["+sw_test_timeout_ns=30_000_000", "+en_scb_tl_err_chk=0"]
run_opts: ["+sw_test_timeout_ns=40_000_000", "+en_scb_tl_err_chk=0"]
run_timeout_mins: 120
}
{
Expand Down

0 comments on commit 2123499

Please sign in to comment.