[verilator/jtag] Update jtag support for verilator

Update dmi dpi for configurable id.
Add jtag interface into opentitanlib verilator transport.
Update verilator jtag configuration files.

Signed-off-by: Daniel Beitel <[email protected]>

hw/dv/dpi/dmidpi/dmidpi.c

@@ -86,6 +86,7 @@ struct dmidpi_ctx {
   struct tcp_server_ctx *sock;
   struct jtag_ctx jtag;
   struct dmi_sig_values sig;
+  int id_code;
 };
 
 /**
@@ -101,7 +102,7 @@ static void set_dr_data(struct dmidpi_ctx *ctx) {
       ctx->jtag.dr_length = 1;
       break;
     case IdCode:
-      ctx->jtag.dr_shift_reg = IDCODEVAL;
+      ctx->jtag.dr_shift_reg = ctx->id_code;
       ctx->jtag.dr_length = 32;
       break;
     case DTMCSR:
@@ -374,12 +375,20 @@ static void update_dmi_state(struct dmidpi_ctx *ctx) {
   }
 }
 
-void *dmidpi_create(const char *display_name, int listen_port) {
+void *dmidpi_create(const char *display_name, unsigned int id_code,
+                    int listen_port) {
   // Create context
   struct dmidpi_ctx *ctx =
       (struct dmidpi_ctx *)calloc(1, sizeof(struct dmidpi_ctx));
   assert(ctx);
 
+  // Initialize ID code value
+  if (id_code != 0) {
+    ctx->id_code = id_code;
+  } else {
+    ctx->id_code = IDCODEVAL;
+  }
+
   // Set up socket details
   ctx->sock = tcp_server_create(display_name, listen_port);
   assert(ctx->sock);

hw/dv/dpi/dmidpi/dmidpi.h

@@ -17,10 +17,12 @@ extern "C" {
  * Call from a initial block.
  *
  * @param display_name Name of the interface (for display purposes only)
+ * @param id_code ID of DMI device
  * @param listen_port Port to listen on
  * @return an initialized struct dmidpi_ctx context object
  */
-void *dmidpi_create(const char *display_name, int listen_port);
+void *dmidpi_create(const char *display_name, unsigned int id_code,
+                    int listen_port);
 
 /**
  * Destructor: Close all connections and free all resources

hw/dv/dpi/dmidpi/dmidpi.sv

@@ -4,6 +4,7 @@
 
 module dmidpi #(
   parameter string Name = "dmi0", // name of the interface (display only)
+  parameter int unsigned IdCode = 'h0000_0000, // ID of the DMI device (Use default)
   parameter int ListenPort = 44853 // TCP port to listen on
 )(
   input  bit        clk_i,
@@ -22,7 +23,8 @@ module dmidpi #(
 );
 
   import "DPI-C"
-  function chandle dmidpi_create(input string name, input int listen_port);
+  function chandle dmidpi_create(input string name, input int unsigned id_code,
+                                 input int listen_port);
 
   import "DPI-C"
   function void dmidpi_tick(input chandle ctx, output bit dmi_req_valid,
@@ -38,7 +40,7 @@ module dmidpi #(
   chandle ctx;
 
   initial begin
-    ctx = dmidpi_create(Name, ListenPort);
+    ctx = dmidpi_create(Name, IdCode, ListenPort);
   end
 
   final begin

hw/top_darjeeling/dv/verilator/chip_sim_tb.sv

@@ -70,7 +70,9 @@ module chip_sim_tb (
 
 `ifdef DMIDirectTAP
   // OpenOCD direct DMI TAP
-  bind rv_dm dmidpi u_dmidpi (
+  bind rv_dm dmidpi #(
+    .IdCode('h1000_1cdf)
+  ) u_dmidpi (
     .clk_i,
     .rst_ni         (cio_gpio_rst_n),
     .dmi_req_valid,

sw/host/opentitanlib/src/transport/verilator/transport.rs

@@ -22,11 +22,14 @@ use crate::transport::{
     Capabilities, Capability, Transport, TransportError, TransportInterfaceType,
 };
 use crate::util::parse_int::ParseInt;
+use crate::io::jtag::{Jtag, JtagParams};
+use crate::util::openocd::OpenOcdServer;
 
 pub(crate) struct Inner {
     uart: Option<Rc<dyn Uart>>,
     spi: Option<Rc<dyn Target>>,
     pub gpio: GpioInner,
+    jtag: Option<Rc<dyn Jtag>>,
 }
 
 /// Represents the verilator transport object.
@@ -78,6 +81,7 @@ impl Verilator {
                 gpio,
                 spi: None,
                 uart: None,
+                jtag: None,
             })),
         })
     }
@@ -148,6 +152,14 @@ impl Transport for Verilator {
             Err(TransportError::UnsupportedOperation.into())
         }
     }
+
+    fn jtag(&self, opts: &JtagParams) -> Result<Rc<dyn Jtag>> {
+        let mut inner = self.inner.borrow_mut();
+        if inner.jtag.is_none() {
+            inner.jtag = Some(Rc::new(OpenOcdServer::new(opts)?));
+        }
+        Ok(Rc::clone(inner.jtag.as_ref().unwrap()))
+    }
 }
 
 /// Watch verilator's stdout for a expression or timeout.

util/openocd/board/BUILD

@@ -0,0 +1,8 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+exports_files([
+    "lowrisc-darjeeling-verilator.cfg",
+    "lowrisc-earlgrey-verilator.cfg",
+])

util/openocd/board/lowrisc-darjeeling-verilator.cfg

@@ -4,8 +4,8 @@
 
 # Board configuration file: the Darjeeling chip in a Verilator simulation
 
-source [find interface/sim-jtagdpi.cfg]
-source [find target/lowrisc-darjeeling.cfg]
+source [find util/openocd/interface/sim-jtagdpi.cfg]
+source [find util/openocd/target/lowrisc-darjeeling.cfg]
 
 # Increase timeouts in simulation
 riscv set_command_timeout_sec 120

util/openocd/interface/BUILD

@@ -0,0 +1,7 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+exports_files([
+    "sim-jtagdpi.cfg",
+])

util/openocd/interface/sim-jtagdpi.cfg

@@ -7,5 +7,5 @@
 # SystemVerilog DPI module.
 
 adapter driver remote_bitbang
-remote_bitbang_port 44853
-remote_bitbang_host localhost
+remote_bitbang port 44853
+remote_bitbang host localhost