[soc_dbg_ctrl,rtl] Add status registers that IBEX writes and JTAG reads

Signed-off-by: Robert Schilling <[email protected]>
lowRISC · Dec 6, 2024 · 1e1e061 · 1e1e061
1 parent 76b928f
commit 1e1e061
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diff --git a/hw/ip/soc_dbg_ctrl/data/soc_dbg_ctrl.hjson b/hw/ip/soc_dbg_ctrl/data/soc_dbg_ctrl.hjson
@@ -225,6 +225,59 @@
           }
         ]
       }
+      { name:     "STATUS"
+        desc:     "Debug Status Register"
+        swaccess: "rw"
+        hwaccess: "hro"
+        fields: [
+          { bits: "0"
+            name: "auth_debug_intent_set"
+            desc: ''' 
+                    Status bit indicating whether the debug intent hardware strap
+                    was set. If set, SoC will be treated as under debug and
+                    authorized debug can be enabled to unlock the SoC at desired
+                    debug unlock level
+                  '''
+            resval: "0"
+          }
+          { bits: "4"
+            name: "auth_window_open"
+            desc: ''' 
+                    Status bit that tells whether debug authorization exchange
+                    can take place 
+                    This bit is set when auth_debug_intent_set is 1 and SoC reset
+                    sequence is paused to enable debug authorization exchange
+                  '''
+            resval: "0"
+          }
+          { bits: "5"
+            name: "auth_window_closed"
+            desc: ''' 
+                    Status bit that indicates that SoC reset sequence is
+                    unpaused SoC shall continue to boot and the debug authorization
+                    exchange cannot take place anymore until next reset. Note that
+                    the rest of the SoC reset sequence is triggered by the OT RoT
+                  '''
+            resval: "0"
+          }
+          { bits: "6"
+            name: "auth_unlock_success"
+            desc: ''' 
+                    Status bit indicating whether the unlock protocol 
+                    resulted in a successful unlock at requested level"
+                  '''
+            resval: "0"
+          }
+          { bits: "7"
+            name: "auth_unlock_failed"
+            desc: ''' 
+                    Status bit indicating whether the unlock protocol was
+                    ulted in unlock failure at requested level"
+                  '''
+            resval: "0"
+          }
+        ]
+      }
     ]
     jtag: [
       { name: "JTAG_TRACE_DEBUG_POLICY_CATEGORY"
@@ -278,6 +331,60 @@
           }
         ]
       }
+      { name:     "JTAG_STATUS"
+        desc:     "Debug Status Register"
+        swaccess: "ro"
+        hwaccess: "hwo"
+        hwext:    "true"
+        fields: [
+          { bits: "0"
+            name: "auth_debug_intent_set"
+            desc: ''' 
+                    Status bit indicating whether the debug intent hardware strap
+                    was set. If set, SoC will be treated as under debug and
+                    authorized debug can be enabled to unlock the SoC at desired
+                    debug unlock level"
+                  '''
+            resval: "0"
+          }
+          { bits: "4"
+            name: "auth_window_open"
+            desc: ''' 
+                    Status bit that tells whether debug authorization exchange
+                    can take place 
+                    This bit is set when auth_debug_intent_set is 1 and SoC reset
+                    sequence is paused to enable debug authorization exchange"
+                  '''
+            resval: "0"
+          }
+          { bits: "5"
+            name: "auth_window_closed"
+            desc: ''' 
+                    Status bit that indicates that SoC reset sequence is
+                    unpaused, SoC shall continue to boot and the debug authorization
+                    exchange cannot take place anymore until next reset. Note that
+                    the rest of the SoC reset sequence is triggered by the OT RoT"
+                  '''
+            resval: "0"
+          }
+          { bits: "6"
+            name: "auth_unlock_success"
+            desc: ''' 
+                    Status bit indicating whether the unlock protocol 
+                    resulted in a successful unlock at requested level"
+                  '''
+            resval: "0"
+          }
+          { bits: "7"
+            name: "auth_unlock_failed"
+            desc: ''' 
+                    Status bit indicating whether the unlock protocol was
+                    ulted in unlock failure at requested level"
+                  '''
+            resval: "0"
+          }
+        ]
+      }
       { name: "JTAG_BOOT_STATUS"
         desc: '''
               Debug boot status register that tells important boot state information.

diff --git a/hw/ip/soc_dbg_ctrl/doc/registers.md b/hw/ip/soc_dbg_ctrl/doc/registers.md
@@ -15,6 +15,7 @@ Depending on the configured debug category, a consumer might accept the debug co
 | soc_dbg_ctrl.[`DEBUG_POLICY_RELOCKED`](#debug_policy_relocked)                         | 0xc      |        4 | Debug Policy relocked                                                                                    |
 | soc_dbg_ctrl.[`TRACE_DEBUG_POLICY_CATEGORY`](#trace_debug_policy_category)             | 0x10     |        4 | Trace register to observe the debug category that is either determined by hardware or software.          |
 | soc_dbg_ctrl.[`TRACE_DEBUG_POLICY_VALID_RELOCKED`](#trace_debug_policy_valid_relocked) | 0x14     |        4 | Trace register to observe the valid or relocked state that is either determined by hardware or software. |
+| soc_dbg_ctrl.[`STATUS`](#status)                                                       | 0x18     |        4 | Debug Status Register                                                                                    |
 
 ## ALERT_TEST
 Alert Test Register
@@ -121,14 +122,38 @@ Trace register to observe the valid or relocked state that is either determined
 |  7:4   |   ro   |   0x9   | relocked | The relocked state determined by hardware or software. |
 |  3:0   |   ro   |   0x9   | valid    | The valid state determined by hardware or software.    |
 
+## STATUS
+Debug Status Register
+- Offset: `0x18`
+- Reset default: `0x0`
+- Reset mask: `0xf1`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "auth_debug_intent_set", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "auth_window_open", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auth_window_closed", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auth_unlock_success", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "auth_unlock_failed", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                  | Description                                                                                                                                                                                                                                       |
+|:------:|:------:|:-------:|:----------------------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+|  31:8  |        |         |                       | Reserved                                                                                                                                                                                                                                          |
+|   7    |   rw   |   0x0   | auth_unlock_failed    | Status bit indicating whether the unlock protocol was ulted in unlock failure at requested level"                                                                                                                                                 |
+|   6    |   rw   |   0x0   | auth_unlock_success   | Status bit indicating whether the unlock protocol  resulted in a successful unlock at requested level"                                                                                                                                            |
+|   5    |   rw   |   0x0   | auth_window_closed    | Status bit that indicates that SoC reset sequence is unpaused SoC shall continue to boot and the debug authorization exchange cannot take place anymore until next reset. Note that the rest of the SoC reset sequence is triggered by the OT RoT |
+|   4    |   rw   |   0x0   | auth_window_open      | Status bit that tells whether debug authorization exchange can take place  This bit is set when auth_debug_intent_set is 1 and SoC reset sequence is paused to enable debug authorization exchange                                                |
+|  3:1   |        |         |                       | Reserved                                                                                                                                                                                                                                          |
+|   0    |   rw   |   0x0   | auth_debug_intent_set | Status bit indicating whether the debug intent hardware strap was set. If set, SoC will be treated as under debug and authorized debug can be enabled to unlock the SoC at desired debug unlock level                                             |
+
 ## Summary of the **`jtag`** interface's registers
 
 | Name                                                                                             | Offset   |   Length | Description                                                                                              |
 |:-------------------------------------------------------------------------------------------------|:---------|---------:|:---------------------------------------------------------------------------------------------------------|
 | soc_dbg_ctrl.[`JTAG_TRACE_DEBUG_POLICY_CATEGORY`](#jtag_trace_debug_policy_category)             | 0x0      |        4 | Trace register to observe the debug category that is either determined by hardware or software.          |
 | soc_dbg_ctrl.[`JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED`](#jtag_trace_debug_policy_valid_relocked) | 0x4      |        4 | Trace register to observe the valid or relocked state that is either determined by hardware or software. |
 | soc_dbg_ctrl.[`JTAG_CONTROL`](#jtag_control)                                                     | 0x8      |        4 | JTAG control register to interact with the boot flow.                                                    |
-| soc_dbg_ctrl.[`JTAG_BOOT_STATUS`](#jtag_boot_status)                                             | 0xc      |        4 | Debug Status Register that tells important boot state information.                                       |
+| soc_dbg_ctrl.[`JTAG_STATUS`](#jtag_status)                                                       | 0xc      |        4 | Debug Status Register                                                                                    |
+| soc_dbg_ctrl.[`JTAG_BOOT_STATUS`](#jtag_boot_status)                                             | 0x10     |        4 | Debug boot status register that tells important boot state information.                                  |
+| soc_dbg_ctrl.[`JTAG_TRACE_SOC_DBG_STATE`](#jtag_trace_soc_dbg_state)                             | 0x14     |        4 | Tells the current debug state coming from OTP.                                                           |
 
 ## JTAG_TRACE_DEBUG_POLICY_CATEGORY
 Trace register to observe the debug category that is either determined by hardware or software.
@@ -182,58 +207,127 @@ JTAG control register to interact with the boot flow.
 |  31:1  |        |         |               | Reserved                                            |
 |   0    |   rw   |   0x0   | boot_continue | JTAG bit to stop or continue the boot flow if Ibex. |
 
-## JTAG_BOOT_STATUS
- Debug Status Register that tells important boot state information.
- Note that this information is reflected only if the hw_dft_en signal is true
+## JTAG_STATUS
+Debug Status Register
 - Offset: `0xc`
 - Reset default: `0x0`
-- Reset mask: `0x7ff`
+- Reset mask: `0xf1`
 
 ### Fields
 
 ```wavejson
-{"reg": [{"name": "main_clk_status", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "io_clk_status", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "otp_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lc_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "rom_ctrl_done", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "rom_ctrl_good", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "cpu_fetch_en", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 21}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}
+{"reg": [{"name": "auth_debug_intent_set", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 3}, {"name": "auth_window_open", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "auth_window_closed", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "auth_unlock_success", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "auth_unlock_failed", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}
+```
+
+|  Bits  |  Type  |  Reset  | Name                                                         |
+|:------:|:------:|:-------:|:-------------------------------------------------------------|
+|  31:8  |        |         | Reserved                                                     |
+|   7    |   ro   |   0x0   | [auth_unlock_failed](#jtag_status--auth_unlock_failed)       |
+|   6    |   ro   |   0x0   | [auth_unlock_success](#jtag_status--auth_unlock_success)     |
+|   5    |   ro   |   0x0   | [auth_window_closed](#jtag_status--auth_window_closed)       |
+|   4    |   ro   |   0x0   | [auth_window_open](#jtag_status--auth_window_open)           |
+|  3:1   |        |         | Reserved                                                     |
+|   0    |   ro   |   0x0   | [auth_debug_intent_set](#jtag_status--auth_debug_intent_set) |
+
+### JTAG_STATUS . auth_unlock_failed
+  Status bit indicating whether the unlock protocol was
+  ulted in unlock failure at requested level"
+
+### JTAG_STATUS . auth_unlock_success
+  Status bit indicating whether the unlock protocol 
+  resulted in a successful unlock at requested level"
+
+### JTAG_STATUS . auth_window_closed
+  Status bit that indicates that SoC reset sequence is
+  unpaused, SoC shall continue to boot and the debug authorization
+  exchange cannot take place anymore until next reset. Note that
+  the rest of the SoC reset sequence is triggered by the OT RoT"
+
+### JTAG_STATUS . auth_window_open
+  Status bit that tells whether debug authorization exchange
+  can take place 
+  This bit is set when auth_debug_intent_set is 1 and SoC reset
+  sequence is paused to enable debug authorization exchange"
+
+### JTAG_STATUS . auth_debug_intent_set
+  Status bit indicating whether the debug intent hardware strap
+  was set. If set, SoC will be treated as under debug and
+  authorized debug can be enabled to unlock the SoC at desired
+  debug unlock level"
+
+## JTAG_BOOT_STATUS
+Debug boot status register that tells important boot state information.
+Note that this information is reflected only if the hw_dft_en signal is true.
+- Offset: `0x10`
+- Reset default: `0x0`
+- Reset mask: `0x3ffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "main_clk_status", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "io_clk_status", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "otp_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "lc_done", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "cpu_fetch_en", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "halt_fsm_state", "bits": 7, "attr": ["ro"], "rotate": -90}, {"name": "rom_ctrl_done", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "rom_ctrl_good", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}
 ```
 
 |  Bits  |  Type  |  Reset  | Name                                                  |
 |:------:|:------:|:-------:|:------------------------------------------------------|
-| 31:11  |        |         | Reserved                                              |
-|   10   |   ro   |   0x0   | [cpu_fetch_en](#jtag_boot_status--cpu_fetch_en)       |
-|  9:7   |   ro   |   0x0   | [rom_ctrl_good](#jtag_boot_status--rom_ctrl_good)     |
-|  6:4   |   ro   |   0x0   | [rom_ctrl_done](#jtag_boot_status--rom_ctrl_done)     |
+| 31:18  |        |         | Reserved                                              |
+| 17:15  |   ro   |   0x0   | [rom_ctrl_good](#jtag_boot_status--rom_ctrl_good)     |
+| 14:12  |   ro   |   0x0   | [rom_ctrl_done](#jtag_boot_status--rom_ctrl_done)     |
+|  11:5  |   ro   |   0x0   | [halt_fsm_state](#jtag_boot_status--halt_fsm_state)   |
+|   4    |   ro   |   0x0   | [cpu_fetch_en](#jtag_boot_status--cpu_fetch_en)       |
 |   3    |   ro   |   0x0   | [lc_done](#jtag_boot_status--lc_done)                 |
 |   2    |   ro   |   0x0   | [otp_done](#jtag_boot_status--otp_done)               |
 |   1    |   ro   |   0x0   | [io_clk_status](#jtag_boot_status--io_clk_status)     |
 |   0    |   ro   |   0x0   | [main_clk_status](#jtag_boot_status--main_clk_status) |
 
-### JTAG_BOOT_STATUS . cpu_fetch_en
- Indication from powermanger to IBEX to state code execution
-
 ### JTAG_BOOT_STATUS . rom_ctrl_good
- Rom control integrity check status; One bit corresponding to each ROM 
- ROM0 = base ROM 
- ROM1 = second ROM partition
- ROM2 = the continue boot inidcaiton form IBEX halt FSM socdbg_ctrl module - 
+  Rom control integrity check status; One bit corresponding to each ROM 
+  ROM0 = base ROM 
+  ROM1 = second ROM partition
+  ROM2 = the continue boot inidcaiton form IBEX halt FSM socdbg_ctrl module - 
         leverages pwrmgr ROM controler inputs to halt boot sequence
 
 ### JTAG_BOOT_STATUS . rom_ctrl_done
- Rom control initialization done; One bit corresponding to each ROM 
- ROM0 = base ROM 
- ROM1 = second ROM partition
- ROM2 = the continue boot inidcaiton form IBEX halt FSM socdbg_ctrl module - 
+  Rom control initialization done; One bit corresponding to each ROM 
+  ROM0 = base ROM 
+  ROM1 = second ROM partition
+  ROM2 = the continue boot inidcaiton form IBEX halt FSM socdbg_ctrl module - 
         leverages pwrmgr ROM controler inputs to halt boot sequence
 
+### JTAG_BOOT_STATUS . halt_fsm_state
+The state of the halt state FSM.
+
+### JTAG_BOOT_STATUS . cpu_fetch_en
+  Indication from powermanger to IBEX to state code execution
+
 ### JTAG_BOOT_STATUS . lc_done
- Lifecycle controller initialization done; LC policy is decoded and set
+  Lifecycle controller initialization done; LC policy is decoded and set
 
 ### JTAG_BOOT_STATUS . otp_done
- OTP controller initialization complete
+  OTP controller initialization complete
 
 ### JTAG_BOOT_STATUS . io_clk_status
- Status of the IO Clock activation
+  Status of the IO Clock activation
 
 ### JTAG_BOOT_STATUS . main_clk_status
- Status of the main clock activation
+  Status of the main clock activation
+
+## JTAG_TRACE_SOC_DBG_STATE
+Tells the current debug state coming from OTP.
+Note that this information is reflected only if the hw_dft_en signal is true.
+- Offset: `0x14`
+- Reset default: `0x0`
+- Reset mask: `0xffffffff`
+
+### Fields
+
+```wavejson
+{"reg": [{"name": "soc_dbg_state", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
+```
+
+|  Bits  |  Type  |  Reset  | Name          | Description              |
+|:------:|:------:|:-------:|:--------------|:-------------------------|
+|  31:0  |   ro   |   0x0   | soc_dbg_state | The current debug state. |
 
 
 <!-- END CMDGEN -->
diff --git a/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl.sv b/hw/ip/soc_dbg_ctrl/rtl/soc_dbg_ctrl.sv
@@ -244,6 +244,10 @@ module soc_dbg_ctrl
   assign jtag_hw2reg.jtag_trace_debug_policy_valid_relocked.relocked.de = 1'b1;
   assign jtag_hw2reg.jtag_trace_debug_policy_valid_relocked.relocked.d  = soc_dbg_policy_q.relocked;
 
+  // The status register is written by IBEX firmware and is reflected into the JTAG status register.
+  // The JTAG user shall query this status register.
+  assign jtag_hw2reg.jtag_status = socdbg_ctrl_hw2reg_jtag_status_reg_t'(core_reg2hw.status);
+
   always_comb  begin
     jtag_hw2reg.jtag_boot_status = '0;
     jtag_hw2reg.jtag_trace_soc_dbg_state = '0;