[primgen] Fix parameters in a primgen template

It turns out that the existing code would give something of this form:

    module prim_foo #(param1, param2) (arg1, arg2);
      parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
    endmodule

Unfortunately, SystemVerilog doesn't actually allow you to declare two
lists of parameters like this. The presence of the #(param1, param2)
list means that the Impl line gets turned into a localparam.

Annoyingly, JasperGold prints out a warning (telling the
user that what they expected to be a parameter is now a localparam).
This patch changes the generated code to match: Impl is now declared
as a localparam, so JasperGold needn't tell us!

Signed-off-by: Rupert Swarbrick <[email protected]>

hw/ip/prim/rtl/prim_onehot_check.sv

@@ -144,7 +144,7 @@ module prim_onehot_check #(
   `ifndef PRIM_DEFAULT_IMPL
     `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
   `endif
-  parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+  localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
 
   logic unused_assert_connected;
   // TODO(#13337): only check generic for now. The path of this prim in other Impl may differ

hw/ip/prim/util/primgen/abstract_prim.sv.tpl

@@ -24,7 +24,7 @@ ${module_header_params}
   ${module_header_ports}
 );
 % if num_techlibs > 1:
-  parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+  localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
 % endif
 
 ${instances}