[hw,top,clkmgr,rtl] Change clock configuration to 1000/250/62.5MHz

Signed-off-by: Robert Schilling <[email protected]>

hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson

@@ -36,13 +36,13 @@
       {
         name: main
         aon: no
-        freq: "100000000"
+        freq: "1000000000"
         ref: false
       }
       {
         name: io
         aon: no
-        freq: "96000000"
+        freq: "1000000000"
         ref: false
       }
       {
@@ -63,15 +63,15 @@
       {
         name: io_div2
         aon: no
-        freq: "48000000"
+        freq: "500000000"
         ref: false
         div: "2"
         src: io
       }
       {
         name: io_div4
         aon: no
-        freq: "24000000"
+        freq: "250000000"
         ref: false
         div: "4"
         src: io

hw/top_darjeeling/data/top_darjeeling.hjson

@@ -46,8 +46,8 @@
     // freq: Absolute frequency of clk in Hz
     // ref: indicates the clock is used as a reference for measurement.
     srcs: [
-      { name: "main", aon: "no",  freq: "100000000" }
-      { name: "io",   aon: "no",  freq: "96000000" }
+      { name: "main", aon: "no",  freq: "1000000000" }
+      { name: "io",   aon: "no",  freq: "1000000000" }
       { name: "usb",  aon: "no",  freq: "48000000" }
       { name: "aon",  aon: "yes", freq: "200000", ref: true}
     ],
@@ -60,8 +60,8 @@
     // src:  From which clock source is the clock derived
     // div:  Ratio between derived clock and source clock
     derived_srcs: [
-      { name: "io_div2", aon: "no", div: 2, src: "io", freq: "48000000" }
-      { name: "io_div4", aon: "no", div: 4, src: "io", freq: "24000000" }
+      { name: "io_div2", aon: "no", div: 2, src: "io", freq: "500000000" }
+      { name: "io_div4", aon: "no", div: 4, src: "io", freq: "250000000" }
     ],
 
     // Clock Group attributes

hw/top_darjeeling/dv/autogen/tb__xbar_connect.sv

@@ -232,11 +232,11 @@ initial begin
     xbar_clk_rst_if.wait_for_reset(.wait_posedge(1'b0));
 
     clk_rst_if_main.set_active(.drive_rst_n_val(0));
-    clk_rst_if_main.set_freq_khz(100000000 / 1000);
+    clk_rst_if_main.set_freq_khz(1000000000 / 1000);
     clk_rst_if_usb.set_active(.drive_rst_n_val(0));
     clk_rst_if_usb.set_freq_khz(48000000 / 1000);
     clk_rst_if_io_div4.set_active(.drive_rst_n_val(0));
-    clk_rst_if_io_div4.set_freq_khz(24000000 / 1000);
+    clk_rst_if_io_div4.set_freq_khz(250000000 / 1000);
 
   end
 end

hw/top_darjeeling/dv/env/seq_lib/chip_sw_power_virus_vseq.sv

@@ -123,8 +123,8 @@ class chip_sw_power_virus_vseq extends chip_sw_base_vseq;
 
     // Wait for max-power indicator GPIO pin to go up.
     wait (cfg.chip_vif.dios[top_darjeeling_pkg::DioPadGpio0]);
-    // Wait for 10 clock cycles.
-    cfg.clk_rst_vif.wait_clks(10);
+    // Wait for 15 clock cycles.
+    cfg.clk_rst_vif.wait_clks(15);
 
     `_DV_PROBE_AND_CHECK_IDLE(spi_device_cio_csb_i, 1'b1)
     `_DV_PROBE_AND_CHECK_IDLE(spi_host_0_cio_csb_o, 1'b1)

hw/top_darjeeling/dv/env/seq_lib/chip_sw_uart_rand_baudrate_vseq.sv

@@ -34,8 +34,8 @@ class chip_sw_uart_rand_baudrate_vseq extends chip_sw_uart_tx_rx_vseq;
         uart_clk_freq_khz = uart_clk_freq_khz * 2;  // div2
       end
     end else begin
-      // internal uart bus clock is 24Mhz
-      uart_clk_freq_khz = 24_000;
+      // internal uart bus clock is 250Mhz
+      uart_clk_freq_khz = 250_000;
     end
   endfunction
 

hw/top_darjeeling/ip/clkmgr/data/autogen/clkmgr.hjson

@@ -597,17 +597,17 @@
       storage_err_alert: "fatal_fault",
       fields: [
         {
-          bits: "9:0",
+          bits: "13:0",
           name: "HI",
           desc: "Max threshold for io measurement",
-          resval: "490"
+          resval: "5010"
         },
 
         {
-          bits: "19:10",
+          bits: "27:14",
           name: "LO",
           desc: "Min threshold for io measurement",
-          resval: "470"
+          resval: "4990"
         },
       ]
     },
@@ -651,17 +651,17 @@
       storage_err_alert: "fatal_fault",
       fields: [
         {
-          bits: "8:0",
+          bits: "12:0",
           name: "HI",
           desc: "Max threshold for io_div2 measurement",
-          resval: "250"
+          resval: "2510"
         },
 
         {
-          bits: "17:9",
+          bits: "25:13",
           name: "LO",
           desc: "Min threshold for io_div2 measurement",
-          resval: "230"
+          resval: "2490"
         },
       ]
     },
@@ -705,17 +705,17 @@
       storage_err_alert: "fatal_fault",
       fields: [
         {
-          bits: "7:0",
+          bits: "11:0",
           name: "HI",
           desc: "Max threshold for io_div4 measurement",
-          resval: "130"
+          resval: "1260"
         },
 
         {
-          bits: "15:8",
+          bits: "23:12",
           name: "LO",
           desc: "Min threshold for io_div4 measurement",
-          resval: "110"
+          resval: "1240"
         },
       ]
     },
@@ -759,17 +759,17 @@
       storage_err_alert: "fatal_fault",
       fields: [
         {
-          bits: "9:0",
+          bits: "13:0",
           name: "HI",
           desc: "Max threshold for main measurement",
-          resval: "510"
+          resval: "5010"
         },
 
         {
-          bits: "19:10",
+          bits: "27:14",
           name: "LO",
           desc: "Min threshold for main measurement",
-          resval: "490"
+          resval: "4990"
         },
       ]
     },

hw/top_darjeeling/ip/clkmgr/rtl/autogen/clkmgr.sv

@@ -573,7 +573,7 @@
   end
 
   clkmgr_meas_chk #(
-    .Cnt(960),
+    .Cnt(10000),
     .RefCnt(1)
   ) u_io_meas (
     .clk_i,
@@ -600,7 +600,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(480),
+    .Cnt(5000),
     .RefCnt(1)
   ) u_io_div2_meas (
     .clk_i,
@@ -627,7 +627,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(240),
+    .Cnt(2500),
     .RefCnt(1)
   ) u_io_div4_meas (
     .clk_i,
@@ -654,7 +654,7 @@
 
 
   clkmgr_meas_chk #(
-    .Cnt(1000),
+    .Cnt(10000),
     .RefCnt(1)
   ) u_main_meas (
     .clk_i,

hw/top_darjeeling/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv

@@ -83,10 +83,10 @@ package clkmgr_reg_pkg;
 
   typedef struct packed {
     struct packed {
-      logic [9:0] q;
+      logic [13:0] q;
     } hi;
     struct packed {
-      logic [9:0] q;
+      logic [13:0] q;
     } lo;
   } clkmgr_reg2hw_io_meas_ctrl_shadowed_reg_t;
 
@@ -96,10 +96,10 @@ package clkmgr_reg_pkg;
 
   typedef struct packed {
     struct packed {
-      logic [8:0]  q;
+      logic [12:0] q;
     } hi;
     struct packed {
-      logic [8:0]  q;
+      logic [12:0] q;
     } lo;
   } clkmgr_reg2hw_io_div2_meas_ctrl_shadowed_reg_t;
 
@@ -109,10 +109,10 @@ package clkmgr_reg_pkg;
 
   typedef struct packed {
     struct packed {
-      logic [7:0]  q;
+      logic [11:0] q;
     } hi;
     struct packed {
-      logic [7:0]  q;
+      logic [11:0] q;
     } lo;
   } clkmgr_reg2hw_io_div4_meas_ctrl_shadowed_reg_t;
 
@@ -122,10 +122,10 @@ package clkmgr_reg_pkg;
 
   typedef struct packed {
     struct packed {
-      logic [9:0] q;
+      logic [13:0] q;
     } hi;
     struct packed {
-      logic [9:0] q;
+      logic [13:0] q;
     } lo;
   } clkmgr_reg2hw_main_meas_ctrl_shadowed_reg_t;
 
@@ -271,20 +271,20 @@ package clkmgr_reg_pkg;
 
   // Register -> HW type
   typedef struct packed {
-    clkmgr_reg2hw_alert_test_reg_t alert_test; // [139:136]
-    clkmgr_reg2hw_extclk_ctrl_reg_t extclk_ctrl; // [135:128]
-    clkmgr_reg2hw_jitter_enable_reg_t jitter_enable; // [127:124]
-    clkmgr_reg2hw_clk_enables_reg_t clk_enables; // [123:120]
-    clkmgr_reg2hw_clk_hints_reg_t clk_hints; // [119:116]
-    clkmgr_reg2hw_measure_ctrl_regwen_reg_t measure_ctrl_regwen; // [115:115]
-    clkmgr_reg2hw_io_meas_ctrl_en_reg_t io_meas_ctrl_en; // [114:111]
-    clkmgr_reg2hw_io_meas_ctrl_shadowed_reg_t io_meas_ctrl_shadowed; // [110:91]
-    clkmgr_reg2hw_io_div2_meas_ctrl_en_reg_t io_div2_meas_ctrl_en; // [90:87]
-    clkmgr_reg2hw_io_div2_meas_ctrl_shadowed_reg_t io_div2_meas_ctrl_shadowed; // [86:69]
-    clkmgr_reg2hw_io_div4_meas_ctrl_en_reg_t io_div4_meas_ctrl_en; // [68:65]
-    clkmgr_reg2hw_io_div4_meas_ctrl_shadowed_reg_t io_div4_meas_ctrl_shadowed; // [64:49]
-    clkmgr_reg2hw_main_meas_ctrl_en_reg_t main_meas_ctrl_en; // [48:45]
-    clkmgr_reg2hw_main_meas_ctrl_shadowed_reg_t main_meas_ctrl_shadowed; // [44:25]
+    clkmgr_reg2hw_alert_test_reg_t alert_test; // [171:168]
+    clkmgr_reg2hw_extclk_ctrl_reg_t extclk_ctrl; // [167:160]
+    clkmgr_reg2hw_jitter_enable_reg_t jitter_enable; // [159:156]
+    clkmgr_reg2hw_clk_enables_reg_t clk_enables; // [155:152]
+    clkmgr_reg2hw_clk_hints_reg_t clk_hints; // [151:148]
+    clkmgr_reg2hw_measure_ctrl_regwen_reg_t measure_ctrl_regwen; // [147:147]
+    clkmgr_reg2hw_io_meas_ctrl_en_reg_t io_meas_ctrl_en; // [146:143]
+    clkmgr_reg2hw_io_meas_ctrl_shadowed_reg_t io_meas_ctrl_shadowed; // [142:115]
+    clkmgr_reg2hw_io_div2_meas_ctrl_en_reg_t io_div2_meas_ctrl_en; // [114:111]
+    clkmgr_reg2hw_io_div2_meas_ctrl_shadowed_reg_t io_div2_meas_ctrl_shadowed; // [110:85]
+    clkmgr_reg2hw_io_div4_meas_ctrl_en_reg_t io_div4_meas_ctrl_en; // [84:81]
+    clkmgr_reg2hw_io_div4_meas_ctrl_shadowed_reg_t io_div4_meas_ctrl_shadowed; // [80:57]
+    clkmgr_reg2hw_main_meas_ctrl_en_reg_t main_meas_ctrl_en; // [56:53]
+    clkmgr_reg2hw_main_meas_ctrl_shadowed_reg_t main_meas_ctrl_shadowed; // [52:25]
     clkmgr_reg2hw_usb_meas_ctrl_en_reg_t usb_meas_ctrl_en; // [24:21]
     clkmgr_reg2hw_usb_meas_ctrl_shadowed_reg_t usb_meas_ctrl_shadowed; // [20:3]
     clkmgr_reg2hw_fatal_err_code_reg_t fatal_err_code; // [2:0]
@@ -374,13 +374,13 @@ package clkmgr_reg_pkg;
     4'b 0001, // index[ 8] CLKMGR_CLK_HINTS_STATUS
     4'b 0001, // index[ 9] CLKMGR_MEASURE_CTRL_REGWEN
     4'b 0001, // index[10] CLKMGR_IO_MEAS_CTRL_EN
-    4'b 0111, // index[11] CLKMGR_IO_MEAS_CTRL_SHADOWED
+    4'b 1111, // index[11] CLKMGR_IO_MEAS_CTRL_SHADOWED
     4'b 0001, // index[12] CLKMGR_IO_DIV2_MEAS_CTRL_EN
-    4'b 0111, // index[13] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED
+    4'b 1111, // index[13] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED
     4'b 0001, // index[14] CLKMGR_IO_DIV4_MEAS_CTRL_EN
-    4'b 0011, // index[15] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED
+    4'b 0111, // index[15] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED
     4'b 0001, // index[16] CLKMGR_MAIN_MEAS_CTRL_EN
-    4'b 0111, // index[17] CLKMGR_MAIN_MEAS_CTRL_SHADOWED
+    4'b 1111, // index[17] CLKMGR_MAIN_MEAS_CTRL_SHADOWED
     4'b 0001, // index[18] CLKMGR_USB_MEAS_CTRL_EN
     4'b 0111, // index[19] CLKMGR_USB_MEAS_CTRL_SHADOWED
     4'b 0011, // index[20] CLKMGR_RECOV_ERR_CODE