[silicon_creator] Port retention_ram driver to DT

Signed-off-by: Amaury Pouly <[email protected]>
lowRISC · Nov 26, 2024 · 1084ba7 · 1084ba7
1 parent 9c614ae
commit 1084ba7
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Showing 2 changed files with 10 additions and 16 deletions.
diff --git a/sw/device/silicon_creator/lib/drivers/BUILD b/sw/device/silicon_creator/lib/drivers/BUILD
@@ -532,7 +532,8 @@ cc_library(
     hdrs = ["retention_sram.h"],
     deps = [
         "//hw/top:sram_ctrl_c_regs",
-        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//hw/top:top_lib",
+        "//hw/top:devicetables",
         "//sw/device/lib/base:abs_mmio",
         "//sw/device/lib/base:macros",
         "//sw/device/lib/base:memory",

diff --git a/sw/device/silicon_creator/lib/drivers/retention_sram.c b/sw/device/silicon_creator/lib/drivers/retention_sram.c
@@ -9,32 +9,24 @@
 #include "sw/device/lib/base/abs_mmio.h"
 #include "sw/device/lib/base/memory.h"
 
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
 #include "sram_ctrl_regs.h"  // Generated.
+#include "devicetables.h"
 
-enum {
-  /**
-   * Base address of retention SRAM control registers.
-   */
-  kBase = TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR,
-};
-
-static_assert(kRetentionSramBase == TOP_EARLGREY_RAM_RET_AON_BASE_ADDR,
-              "Unexpected retention SRAM base address.");
-static_assert(sizeof(retention_sram_t) == TOP_EARLGREY_RAM_RET_AON_SIZE_BYTES,
-              "Unexpected retention SRAM size.");
+static const dt_sram_ctrl_t *kSramCtrlDt = &kDtSramCtrl[kDtIndexSramCtrlRetAon];
 
 void retention_sram_clear(void) {
   memset(retention_sram_get(), 0, sizeof(retention_sram_t));
 }
 
 void retention_sram_init(void) {
   uint32_t reg = bitfield_bit32_write(0, SRAM_CTRL_CTRL_INIT_BIT, true);
-  abs_mmio_write32(kBase + SRAM_CTRL_CTRL_REG_OFFSET, reg);
+  uint32_t base = dt_sram_ctrl_reg_block(kSramCtrlDt, kDtSramCtrlRegBlockRegs);
+  abs_mmio_write32(base + SRAM_CTRL_CTRL_REG_OFFSET, reg);
 }
 
 void retention_sram_readback_enable(uint32_t en) {
-  abs_mmio_write32(kBase + SRAM_CTRL_READBACK_REG_OFFSET, en);
+  uint32_t base = dt_sram_ctrl_reg_block(kSramCtrlDt, kDtSramCtrlRegBlockRegs);
+  abs_mmio_write32(base + SRAM_CTRL_READBACK_REG_OFFSET, en);
 }
 
 void retention_sram_scramble(void) {
@@ -43,7 +35,8 @@ void retention_sram_scramble(void) {
   uint32_t ctrl = 0;
   ctrl = bitfield_bit32_write(ctrl, SRAM_CTRL_CTRL_RENEW_SCR_KEY_BIT, true);
   ctrl = bitfield_bit32_write(ctrl, SRAM_CTRL_CTRL_INIT_BIT, true);
-  abs_mmio_write32(kBase + SRAM_CTRL_CTRL_REG_OFFSET, ctrl);
+  uint32_t base = dt_sram_ctrl_reg_block(kSramCtrlDt, kDtSramCtrlRegBlockRegs);
+  abs_mmio_write32(base + SRAM_CTRL_CTRL_REG_OFFSET, ctrl);
 }
 
 rom_error_t retention_sram_check_version(void) {