[prim,earlgrey,fpga] Add specialized ram_1p prim

Add a specialized ram_1p prim for the prim_xilinx library. This prim
adds some prim_xilinx-specific parameters to enable selecting particular
layouts for embedded memories. The intention is to have the top-level
override the parameters with hierarchical assignment.

This feature is intended for use with memories that are too wide to fit
in updatemem's capabilities (where splicing is required). The flash info
pages are one such type, since updatemem can only handle up to 64-bit
wide items, and the info page array is 76 bits wide. Synthesis chooses
the most efficient layout of the memories, but the layout is awkward for
handling splices.

Force earlgrey's flash info data and metadata into separate arrays for
the FPGA.

Signed-off-by: Alexander Williams <[email protected]>

hw/ip/prim_xilinx/lint/prim_xilinx_ram_1p.vlt

@@ -0,0 +1 @@
+

hw/ip/prim_xilinx/lint/prim_xilinx_ram_1p.waiver

@@ -0,0 +1 @@
+

hw/ip/prim_xilinx/prim_xilinx_default_pkg.core

@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim_xilinx:prim_xilinx_default_pkg"
+description: "Single port RAM"
+virtual:
+  - lowrisc:prim_xilinx:prim_xilinx_pkg
+filesets:
+  files_rtl:
+    files:
+      - rtl/prim_xilinx_pkg.sv
+    file_type: systemVerilogSource
+
+targets:
+  default: &default_target
+    filesets:
+      - files_rtl

hw/ip/prim_xilinx/prim_xilinx_ram_1p.core

@@ -0,0 +1,47 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim_xilinx:ram_1p"
+description: "Single port RAM"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:assert
+      - lowrisc:prim:ram_1p_pkg
+      - lowrisc:prim_xilinx:prim_xilinx_pkg
+      - lowrisc:prim_generic:ram_1p
+      - lowrisc:prim:util_memload
+    files:
+      - rtl/prim_xilinx_ram_1p.sv
+    file_type: systemVerilogSource
+
+  files_verilator_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_xilinx_ram_1p.vlt
+    file_type: vlt
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_xilinx_ram_1p.waiver
+    file_type: waiver
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+targets:
+  default:
+    filesets:
+      - tool_verilator   ? (files_verilator_waiver)
+      - tool_ascentlint  ? (files_ascentlint_waiver)
+      - tool_veriblelint ? (files_veriblelint_waiver)
+      - files_rtl

hw/ip/prim_xilinx/rtl/prim_xilinx_pkg.sv

@@ -0,0 +1,11 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package prim_xilinx_pkg;
+
+  function int get_ram_max_width(int width, int depth);
+    return 0;
+  endfunction
+
+endpackage : prim_xilinx_pkg

hw/ip/prim_xilinx/rtl/prim_xilinx_ram_1p.sv

@@ -0,0 +1,77 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Synchronous single-port SRAM model
+
+`include "prim_assert.sv"
+
+module prim_xilinx_ram_1p import prim_ram_1p_pkg::*; #(
+  parameter  int Width           = 32, // bit
+  parameter  int Depth           = 128,
+  parameter  int DataBitsPerMask = 1, // Number of data bits per bit of write mask
+  parameter      MemInitFile     = "", // VMEM file to initialize the memory with
+
+  localparam int Aw              = $clog2(Depth)  // derived parameter
+) (
+  input  logic             clk_i,
+
+  input  logic             req_i,
+  input  logic             write_i,
+  input  logic [Aw-1:0]    addr_i,
+  input  logic [Width-1:0] wdata_i,
+  input  logic [Width-1:0] wmask_i,
+  output logic [Width-1:0] rdata_o, // Read data. Data is returned one cycle after req_i is high.
+  input ram_1p_cfg_t       cfg_i
+);
+
+  localparam int PrimMaxWidth = prim_xilinx_pkg::get_ram_max_width(Width, Depth);
+
+  if (PrimMaxWidth <= 0) begin : gen_generic
+    prim_generic_ram_1p #(
+      .Width(Width),
+      .Depth(Depth),
+      .DataBitsPerMask(DataBitsPerMask),
+      .MemInitFile(MemInitFile)
+    ) u_ram_1p (
+      .*
+    );
+  end else begin : gen
+    logic wr_en;
+    assign wr_en = write_i & wmask_i[0];
+
+    logic unused_cfg_i;
+    assign unused_cfg_i = cfg_i;
+
+    for (genvar k = 0; k < Width; k = k + PrimMaxWidth) begin : split
+      localparam int PrimWidth = ((Width - k) > PrimMaxWidth) ? PrimMaxWidth : Width - k;
+      localparam PrimMemoryInitFile = (MemInitFile != "") ? MemInitFile : "none";
+
+      xpm_memory_spram #(
+        .ADDR_WIDTH_A(Aw),
+        .BYTE_WRITE_WIDTH_A(PrimWidth), // Masks are not supported
+        .MEMORY_INIT_FILE(PrimMemoryInitFile),
+        .MEMORY_SIZE(Depth * PrimWidth),
+        .READ_DATA_WIDTH_A(PrimWidth),
+        .READ_LATENCY_A(1),
+        .USE_MEM_INIT_MMI(1),
+        .WRITE_DATA_WIDTH_A(PrimWidth)
+      ) u_ram_1p (
+        .clka(clk_i),
+        .addra(addr_i),
+        .dbiterra(),
+        .dina(wdata_i[k +: PrimWidth]),
+        .douta(rdata_o[k +: PrimWidth]),
+        .ena(req_i),
+        .injectdbiterra(1'b0),
+        .injectsbiterra(1'b0),
+        .regcea(1'b1),
+        .rsta(1'b0),
+        .sbiterra(),
+        .sleep(1'b0),
+        .wea(wr_en)
+      );
+    end
+  end
+
+endmodule

hw/ip/prim_xilinx/rtl/prim_xilinx_rom.sv

@@ -0,0 +1,52 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`include "prim_assert.sv"
+
+module prim_xilinx_rom import prim_rom_pkg::*; #(
+  parameter  int Width       = 32,
+  parameter  int Depth       = 2048, // 8kB default
+  parameter      MemInitFile = "", // VMEM file to initialize the memory with
+
+  localparam int Aw          = $clog2(Depth)
+) (
+  input  logic             clk_i,
+  input  logic             req_i,
+  input  logic [Aw-1:0]    addr_i,
+  output logic [Width-1:0] rdata_o,
+  input rom_cfg_t          cfg_i
+);
+
+  localparam PrimMemoryInitFile = (MemInitFile != "") ? MemInitFile : "none";
+  localparam PrimMemoryOptimization = (MemInitFile != "") ? "false" : "true";
+
+  xpm_memory_sprom #(
+     .ADDR_WIDTH_A(Aw),
+     .MEMORY_INIT_FILE(PrimMemoryInitFile),
+     .MEMORY_OPTIMIZATION(PrimMemoryOptimization),
+     .MEMORY_SIZE(Depth * Width),
+     .READ_DATA_WIDTH_A(Width),
+     .READ_LATENCY_A(1),
+     .USE_MEM_INIT_MMI(1)
+  ) u_rom (
+    .clka(clk_i),
+    .addra(addr_i),
+    .dbiterra(),
+    .douta(rdata_o[k +: PrimWidth]),
+    .ena(req_i),
+    .injectdbiterra(1'b0),
+    .injectsbiterra(1'b0),
+    .regcea(1'b1),
+    .rsta(1'b0),
+    .sbiterra(),
+    .sleep(1'b0)
+  );
+
+  ////////////////
+  // ASSERTIONS //
+  ////////////////
+
+  // Control Signals should never be X
+  `ASSERT(noXOnCsI, !$isunknown(req_i), clk_i, '0)
+endmodule

hw/ip/prim_xilinx_ultrascale/prim_xilinx_ultrascale_ram_1p.core

@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim_xilinx_ultrascale:ram_1p"
+description: "Single port RAM"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim_xilinx:ram_1p
+    files:
+      - rtl/prim_xilinx_ultrascale_ram_1p.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_rtl

hw/ip/prim_xilinx_ultrascale/rtl/prim_xilinx_ultrascale_ram_1p.sv

@@ -0,0 +1,30 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Synchronous single-port SRAM model
+
+`include "prim_assert.sv"
+
+module prim_xilinx_ram_1p import prim_ram_1p_pkg::*; #(
+  parameter  int Width           = 32, // bit
+  parameter  int Depth           = 128,
+  parameter  int DataBitsPerMask = 1, // Number of data bits per bit of write mask
+  parameter      MemInitFile     = "", // VMEM file to initialize the memory with
+
+  localparam int Aw              = $clog2(Depth)  // derived parameter
+) (
+  input  logic             clk_i,
+
+  input  logic             req_i,
+  input  logic             write_i,
+  input  logic [Aw-1:0]    addr_i,
+  input  logic [Width-1:0] wdata_i,
+  input  logic [Width-1:0] wmask_i,
+  output logic [Width-1:0] rdata_o, // Read data. Data is returned one cycle after req_i is high.
+  input ram_1p_cfg_t       cfg_i
+);
+
+  prim_xilinx_ram_1p #(.*) u_inst (.*);
+
+endmodule

hw/top_earlgrey/chip_earlgrey_cw310.core

@@ -7,6 +7,7 @@ description: "Earl Grey toplevel for the ChipWhisperer CW310 board"
 filesets:
   files_rtl_cw310:
     depend:
+      - lowrisc:prim_xilinx:earlgrey_xilinx_prim_pkg
       - lowrisc:systems:top_earlgrey:0.1
       - lowrisc:systems:top_earlgrey_pkg
       - lowrisc:systems:ast
@@ -23,7 +24,6 @@ filesets:
       - data/clocks.xdc
       - data/pins_cw310.xdc
       - data/placement.xdc
-      - data/synth.xdc
     file_type: xdc
 
   files_tcl:

hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core

@@ -7,6 +7,7 @@ description: "Earl Grey toplevel for the ChipWhisperer CW310 board's hyperdebug
 filesets:
   files_rtl_cw310:
     depend:
+      - lowrisc:prim_xilinx:earlgrey_xilinx_prim_pkg
       - lowrisc:systems:top_earlgrey:0.1
       - lowrisc:systems:top_earlgrey_pkg
       - lowrisc:systems:ast
@@ -25,7 +26,6 @@ filesets:
       # same as lowrisc:systems:chip_earlgrey_cw310.
       - data/pins_cw310_hyperdebug.xdc
       - data/placement.xdc
-      - data/synth.xdc
     file_type: xdc
 
   files_tcl:

hw/top_earlgrey/chip_earlgrey_cw340.core

@@ -7,6 +7,7 @@ description: "Earl Grey toplevel for the ChipWhisperer CW340 board"
 filesets:
   files_rtl_cw340:
     depend:
+      - lowrisc:prim_xilinx_ultrascale:earlgrey_xilinx_ultrascale_prim_pkg
       - lowrisc:systems:top_earlgrey:0.1
       - lowrisc:systems:top_earlgrey_pkg
       - lowrisc:systems:ast
@@ -22,7 +23,6 @@ filesets:
     files:
       - data/clocks_cw341.xdc
       - data/pins_cw341.xdc
-      - data/synth.xdc
     file_type: xdc
 
   files_tcl:

hw/top_earlgrey/earlgrey_xilinx_prim_pkg.core

@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim_xilinx:earlgrey_xilinx_prim_pkg"
+description: "Single port RAM"
+virtual:
+  - lowrisc:prim_xilinx:prim_xilinx_pkg
+filesets:
+  files_rtl:
+    files:
+      - rtl/prim_xilinx_pkg.sv
+    file_type: systemVerilogSource
+
+targets:
+  default: &default_target
+    filesets:
+      - files_rtl

hw/top_earlgrey/rtl/prim_xilinx_pkg.sv

@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package prim_xilinx_pkg;
+
+  function int get_ram_max_width(int width, int depth);
+    if (width == 76 && depth < 4096) begin
+      return 64;
+    end
+    return 0;
+  endfunction
+
+endpackage : prim_xilinx_pkg