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[prim] Remove primgen and replace with virtual cores #3765

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[prim] Remove primgen and replace with virtual cores

[prim] Remove primgen and replace with virtual cores #3765

Triggered via pull request December 23, 2024 00:41
@a-willa-will
synchronize #23555
a-will:fusesoc-compat
Status Cancelled
Total duration 34m 2s
Artifacts 2

ci.yml

on: pull_request
Lint (quick)
4m 13s
Lint (quick)
Earl Grey for CW310 Hyperdebug  /  Build bitstream
27m 42s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
25s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310  /  Build bitstream
28m 43s
Earl Grey for CW310 / Build bitstream
Lint (slow)
8m 33s
Lint (slow)
Build documentation
5m 28s
Build documentation
Airgapped build
7m 44s
Airgapped build
Verible lint
2m 5s
Verible lint
Run OTBN smoke Test
2m 21s
Run OTBN smoke Test
Run OTBN crypto tests
23m 35s
Run OTBN crypto tests
Verilated English Breakfast
8m 31s
Verilated English Breakfast
Verilated Earl Grey
29m 20s
Verilated Earl Grey
CW305's Bitstream
22m 33s
CW305's Bitstream
Build Docker Containers
2m 35s
Build Docker Containers
Build and test software
21m 52s
Build and test software
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
0s
Verify FPGA jobs
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Annotations

19 errors and 1 warning
Verible lint
Process completed with exit code 1.
Earl Grey for CW340 / Build bitstream
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Verilog style lint of design sources with Verible failed. Run 'util/dvsim/dvsim.py -t veriblelint hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson' and fix all errors.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.
CW305's Bitstream
Process completed with exit code 1.
Verilated Earl Grey
Canceling since a higher priority waiting request for 'CI-refs/pull/23555/merge' exists
Verilated Earl Grey
The operation was canceled.
Earl Grey for CW310 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/23555/merge' exists
Earl Grey for CW310 / Build bitstream
The operation was canceled.
Earl Grey for CW310 Hyperdebug / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/23555/merge' exists
Earl Grey for CW310 Hyperdebug / Build bitstream
The operation was canceled.
Earl Grey for CW340 / Build bitstream
No files were found with the provided path: build-out. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
sw_build_test-test-results
74.7 KB
verilated_englishbreakfast
6.25 MB