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[prim_ram_1p] Ram tiling for sram_ctrl and prim_ram_1p #3753

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[prim_ram_1p] Ram tiling for sram_ctrl and prim_ram_1p

[prim_ram_1p] Ram tiling for sram_ctrl and prim_ram_1p #3753

Triggered via pull request December 21, 2024 13:55
@Razer6Razer6
synchronize #25625
Razer6:ram-cfg-tile
Status Cancelled
Total duration 26m 18s
Artifacts 2

ci.yml

on: pull_request
Lint (quick)
3m 25s
Lint (quick)
Earl Grey for CW310 Hyperdebug  /  Build bitstream
21m 47s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
22m 4s
Earl Grey for CW310 / Build bitstream
Earl Grey for CW340  /  Build bitstream
21m 47s
Earl Grey for CW340 / Build bitstream
Lint (slow)
9m 3s
Lint (slow)
Build documentation
4m 54s
Build documentation
Airgapped build
7m 30s
Airgapped build
Verible lint
1m 4s
Verible lint
Run OTBN smoke Test
1m 27s
Run OTBN smoke Test
Run OTBN crypto tests
20m 50s
Run OTBN crypto tests
Verilated English Breakfast
1m 3s
Verilated English Breakfast
Verilated Earl Grey
3m 44s
Verilated Earl Grey
CW305's Bitstream
21m 49s
CW305's Bitstream
Build Docker Containers
2m 39s
Build Docker Containers
Build and test software
14m 19s
Build and test software
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
0s
Verify FPGA jobs
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21 errors
Verilated English Breakfast
Process completed with exit code 1.
Run OTBN smoke Test
Process completed with exit code 1.
Verilated Earl Grey
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Verilog style lint of design sources with Verible failed. Run 'util/dvsim/dvsim.py -t veriblelint hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson' and fix all errors.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.
CW305's Bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/25625/merge' exists
CW305's Bitstream
The operation was canceled.
Earl Grey for CW340 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/25625/merge' exists
Earl Grey for CW340 / Build bitstream
The operation was canceled.
Earl Grey for CW310 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/25625/merge' exists
Earl Grey for CW310 / Build bitstream
The operation was canceled.
Earl Grey for CW310 Hyperdebug / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/25625/merge' exists
Earl Grey for CW310 Hyperdebug / Build bitstream
The operation was canceled.

Artifacts

Produced during runtime
Name Size
sw_build_test-test-results
75 KB
verilator_earlgrey-test-results
201 Bytes