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[prim] Remove primgen and replace with virtual cores #3590

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[prim] Remove primgen and replace with virtual cores

[prim] Remove primgen and replace with virtual cores #3590

Triggered via pull request December 18, 2024 09:04
@a-willa-will
synchronize #23555
a-will:fusesoc-compat
Status Cancelled
Total duration 12m 36s
Artifacts 4

ci.yml

on: pull_request
Lint (quick)
3m 30s
Lint (quick)
Earl Grey for CW310  /  Build bitstream
6m 2s
Earl Grey for CW310 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
6m 6s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
6m 33s
Earl Grey for CW340 / Build bitstream
Lint (slow)
8m 24s
Lint (slow)
Build documentation
5m 0s
Build documentation
Airgapped build
8m 26s
Airgapped build
Verible lint
1m 4s
Verible lint
Run OTBN smoke Test
1m 38s
Run OTBN smoke Test
Run OTBN crypto tests
8m 29s
Run OTBN crypto tests
Verilated English Breakfast
50s
Verilated English Breakfast
Verilated Earl Grey
3m 27s
Verilated Earl Grey
CW305's Bitstream
5m 38s
CW305's Bitstream
Build Docker Containers
2m 24s
Build Docker Containers
Build and test software
8m 7s
Build and test software
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
CW310 ROM_EXT Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
23s
Verify FPGA jobs
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Annotations

25 errors
Verilated English Breakfast
Process completed with exit code 1.
Verible lint
Process completed with exit code 1.
Run OTBN smoke Test
Process completed with exit code 1.
Verilated Earl Grey
Process completed with exit code 1.
CW305's Bitstream
Process completed with exit code 1.
Earl Grey for CW310 / Build bitstream
Process completed with exit code 1.
Earl Grey for CW310 Hyperdebug / Build bitstream
Process completed with exit code 1.
Earl Grey for CW340 / Build bitstream
Process completed with exit code 1.
Verify FPGA jobs
Process completed with exit code 1.
Verify FPGA jobs
Process completed with exit code 1.
Lint (slow)
Canceling since a higher priority waiting request for 'CI-refs/pull/23555/merge' exists
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
The operation was canceled.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Airgapped build
Canceling since a higher priority waiting request for 'CI-refs/pull/23555/merge' exists
Airgapped build
The operation was canceled.
Build and test software
Canceling since a higher priority waiting request for 'CI-refs/pull/23555/merge' exists
Build and test software
The operation was canceled.
Run OTBN crypto tests
Canceling since a higher priority waiting request for 'CI-refs/pull/23555/merge' exists
Run OTBN crypto tests
The operation was canceled.

Artifacts

Produced during runtime
Name Size
chip_earlgrey_cw310-build-out
27.7 KB
chip_earlgrey_cw310_hyperdebug-build-out
28.5 KB
chip_earlgrey_cw340-build-out
27.8 KB
verilator_earlgrey-test-results
201 Bytes