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[RACL] Implement config parsing, racl_ctrl, and reggen checks #3585

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[RACL] Implement config parsing, racl_ctrl, and reggen checks

[RACL] Implement config parsing, racl_ctrl, and reggen checks #3585

Triggered via pull request December 18, 2024 05:53
@Razer6Razer6
synchronize #25664
Razer6:racl-package
Status Failure
Total duration 2m 56s
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ci.yml

on: pull_request
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Earl Grey for CW310 Hyperdebug  /  Build bitstream
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
Earl Grey for CW310 / Build bitstream
Earl Grey for CW340  /  Build bitstream
Earl Grey for CW340 / Build bitstream
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Build documentation
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Build documentation
Airgapped build
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Airgapped build
Verible lint
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Verible lint
Run OTBN smoke Test
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Run OTBN smoke Test
Run OTBN crypto tests
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Run OTBN crypto tests
Verilated English Breakfast
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Verilated English Breakfast
Verilated Earl Grey
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Verilated Earl Grey
CW305's Bitstream
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CW305's Bitstream
Build Docker Containers
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Build Docker Containers
Build and test software
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Build and test software
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
CW310 ROM_EXT Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
Cache bitstreams to GCP
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Cache bitstreams to GCP
Verify FPGA jobs
24s
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7 errors
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Failed mypy check in hw/ip/otbn/dv/rig.
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Failed mypy check in hw/ip/otbn/dv/otbnsim.
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Failed mypy check in hw/ip/otbn/util.
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Failed mypy check in util/reggen.
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Process completed with exit code 1.
Verify FPGA jobs
Process completed with exit code 1.
Verify FPGA jobs
Process completed with exit code 1.