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Cherry-pick to master: [rom_ext_e2e] Update CI to run ROM_EXT tests on hyper310 #3581

Cherry-pick to master: [rom_ext_e2e] Update CI to run ROM_EXT tests on hyper310

Cherry-pick to master: [rom_ext_e2e] Update CI to run ROM_EXT tests on hyper310 #3581

Re-run triggered December 18, 2024 06:05
Status Success
Total duration 1h 18m 8s
Artifacts 31

ci.yml

on: pull_request
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1m 52s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
3m 36s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310  /  Build bitstream
2m 27s
Earl Grey for CW310 / Build bitstream
Lint (slow)
16m 1s
Lint (slow)
Build documentation
5m 30s
Build documentation
Airgapped build
13m 18s
Airgapped build
Verible lint
1m 26s
Verible lint
Run OTBN smoke Test
2m 49s
Run OTBN smoke Test
Run OTBN crypto tests
22m 37s
Run OTBN crypto tests
Verilated English Breakfast
8m 25s
Verilated English Breakfast
Verilated Earl Grey
1h 17m
Verilated Earl Grey
CW305's Bitstream
22m 14s
CW305's Bitstream
Build Docker Containers
2m 56s
Build Docker Containers
Build and test software
16m 55s
Build and test software
CW310 ROM_EXT Tests  /  FPGA test
8m 29s
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
27m 41s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
38m 4s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
31m 5s
CW310 Manufacturing Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
3m 32s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
49s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
6m 31s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
17m 56s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
3m 56s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
7m 1s
CW340 Manufacturing Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
4m 5s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
40m 7s
CW310 ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
22s
Verify FPGA jobs
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Annotations

12 errors
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
CW305's Bitstream
unable to access 'https://github.com/lowRISC/opentitan/': The requested URL returned error: 503
Earl Grey for CW340 / Build bitstream
error reading section header 'shallow-info'
Earl Grey for CW340 / Build bitstream
RPC failed; HTTP 503 curl 22 The requested URL returned error: 503
Earl Grey for CW340 / Build bitstream
expected flush after ref listing
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
57.9 KB
execute_rom_ext_fpga_tests_cw310-targets
510 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
9.86 KB
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
36.7 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.21 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
179 KB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
6.05 MB
sw_build_test-test-results
61.5 KB
verilator_earlgrey-test-results
8.95 KB