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[RACL] Implement config parsing, racl_ctrl, and reggen checks #3550

[RACL] Implement config parsing, racl_ctrl, and reggen checks

[RACL] Implement config parsing, racl_ctrl, and reggen checks #3550

Triggered via pull request December 17, 2024 15:24
Status Success
Total duration 4h 48m 35s
Artifacts 31

ci.yml

on: pull_request
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1h 15m
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
1h 5m
Earl Grey for CW310 / Build bitstream
Earl Grey for CW340  /  Build bitstream
1h 26m
Earl Grey for CW340 / Build bitstream
Lint (slow)
15m 15s
Lint (slow)
Build documentation
5m 2s
Build documentation
Airgapped build
10m 54s
Airgapped build
Verible lint
1m 8s
Verible lint
Run OTBN smoke Test
2m 27s
Run OTBN smoke Test
Run OTBN crypto tests
20m 55s
Run OTBN crypto tests
Verilated English Breakfast
7m 55s
Verilated English Breakfast
Verilated Earl Grey
1h 21m
Verilated Earl Grey
CW305's Bitstream
25m 12s
CW305's Bitstream
Build Docker Containers
2m 47s
Build Docker Containers
Build and test software
18m 17s
Build and test software
CW310 SiVal Tests  /  FPGA test
25m 21s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
34m 35s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
30m 11s
CW310 Manufacturing Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
5m 13s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
39m 24s
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
6m 39s
CW310 ROM_EXT Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
3m 15s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
47s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
5m 31s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
16m 45s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
3m 53s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
7m 21s
CW340 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
33s
Verify FPGA jobs
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8 errors
Lint (slow)
Countermeasure check failed.
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Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.37 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
58.3 KB
execute_manuf_fpga_tests_cw340-targets
280 Bytes
execute_manuf_fpga_tests_cw340-test-results
17.4 KB
execute_rom_ext_fpga_tests_cw310-targets
379 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
4.96 KB
execute_rom_ext_fpga_tests_cw340-targets
363 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
5.65 KB
execute_rom_fpga_tests_cw310-targets
1.8 KB
execute_rom_fpga_tests_cw310-test-results
46.9 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
36.4 KB
execute_sival_fpga_tests_cw340-targets
502 Bytes
execute_sival_fpga_tests_cw340-test-results
39.9 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.21 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
178 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
435 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
15.8 KB
execute_test_rom_fpga_tests_cw310-targets
312 Bytes
execute_test_rom_fpga_tests_cw310-test-results
2.88 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
45.3 KB
partial-build-bin-chip_earlgrey_cw310
6.02 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
6.05 MB
partial-build-bin-chip_earlgrey_cw340
9.81 MB
sw_build_test-test-results
59.8 KB
verilated_englishbreakfast
6.54 MB
verilator_earlgrey-test-results
9.05 KB