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[rom_ctrl, dv] Removal of a signal to cover cond coverage hole #3549

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[rom_ctrl, dv] Removal of a signal to cover cond coverage hole

[rom_ctrl, dv] Removal of a signal to cover cond coverage hole #3549

Triggered via pull request December 17, 2024 15:04
@KinzaQamarKinzaQamar
synchronize #25682
KinzaQamar:rom_ctrl_fsm_cov
Status Success
Total duration 4h 57m 8s
Artifacts 31

ci.yml

on: pull_request
Lint (quick)
3m 49s
Lint (quick)
Earl Grey for CW310  /  Build bitstream
1h 8m
Earl Grey for CW310 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1h 35m
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
1h 28m
Earl Grey for CW340 / Build bitstream
Lint (slow)
15m 27s
Lint (slow)
Build documentation
5m 18s
Build documentation
Airgapped build
9m 51s
Airgapped build
Verible lint
1m 4s
Verible lint
Run OTBN smoke Test
2m 29s
Run OTBN smoke Test
Run OTBN crypto tests
23m 25s
Run OTBN crypto tests
Verilated English Breakfast
8m 2s
Verilated English Breakfast
Verilated Earl Grey
1h 27m
Verilated Earl Grey
CW305's Bitstream
24m 29s
CW305's Bitstream
Build Docker Containers
2m 45s
Build Docker Containers
Build and test software
16m 4s
Build and test software
CW310 Test ROM Tests  /  FPGA test
4m 37s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
37m 54s
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
5m 54s
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
23m 21s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
32m 7s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
28m 41s
CW310 Manufacturing Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
3m 23s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
50s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
5m 50s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
16m 53s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
4m 25s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
7m 2s
CW340 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
23s
Verify FPGA jobs
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Annotations

8 errors
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.37 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
58 KB
execute_manuf_fpga_tests_cw340-targets
280 Bytes
execute_manuf_fpga_tests_cw340-test-results
17.3 KB
execute_rom_ext_fpga_tests_cw310-targets
379 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
4.91 KB
execute_rom_ext_fpga_tests_cw340-targets
363 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
5.46 KB
execute_rom_fpga_tests_cw310-targets
1.8 KB
execute_rom_fpga_tests_cw310-test-results
46.2 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
36.6 KB
execute_sival_fpga_tests_cw340-targets
502 Bytes
execute_sival_fpga_tests_cw340-test-results
39.6 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.21 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
178 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
435 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
18 KB
execute_test_rom_fpga_tests_cw310-targets
312 Bytes
execute_test_rom_fpga_tests_cw310-test-results
2.84 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
44.4 KB
partial-build-bin-chip_earlgrey_cw310
6.03 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
6.03 MB
partial-build-bin-chip_earlgrey_cw340
9.93 MB
sw_build_test-test-results
60.4 KB
verilated_englishbreakfast
6.54 MB
verilator_earlgrey-test-results
9 KB