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[fpga] Add prim features and tool flow to dump the flash info array cell sites #3367

[fpga] Add prim features and tool flow to dump the flash info array cell sites

[fpga] Add prim features and tool flow to dump the flash info array cell sites #3367

Triggered via pull request December 14, 2024 06:37
Status Success
Total duration 1h 56m 44s
Artifacts 31

ci.yml

on: pull_request
Earl Grey for CW310  /  Build bitstream
1h 6m
Earl Grey for CW310 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
1h 13m
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
1h 28m
Earl Grey for CW340 / Build bitstream
Lint (slow)
12m 50s
Lint (slow)
Build documentation
5m 19s
Build documentation
Airgapped build
9m 0s
Airgapped build
Verible lint
1m 4s
Verible lint
Run OTBN smoke Test
2m 54s
Run OTBN smoke Test
Run OTBN crypto tests
20m 45s
Run OTBN crypto tests
Verilated English Breakfast
7m 58s
Verilated English Breakfast
Verilated Earl Grey
1h 24m
Verilated Earl Grey
CW305's Bitstream
26m 20s
CW305's Bitstream
Build Docker Containers
2m 54s
Build Docker Containers
Build and test software
15m 44s
Build and test software
CW310 Test ROM Tests  /  FPGA test
5m 52s
CW310 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
41m 16s
CW310 ROM Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
8m 38s
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
26m 9s
CW310 SiVal Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
37m 20s
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
32m 19s
CW310 Manufacturing Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
3m 26s
CW340 Test ROM Tests / FPGA test
CW340 ROM Tests  /  FPGA test
47s
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
3m 8s
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
16m 44s
CW340 SiVal Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
3m 42s
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
8m 2s
CW340 Manufacturing Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
22s
Verify FPGA jobs
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8 errors
Lint (slow)
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Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
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Process completed with exit code 1.
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Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.37 MB
execute_manuf_fpga_tests_cw310-targets
623 Bytes
execute_manuf_fpga_tests_cw310-test-results
58.5 KB
execute_manuf_fpga_tests_cw340-targets
280 Bytes
execute_manuf_fpga_tests_cw340-test-results
17.2 KB
execute_rom_ext_fpga_tests_cw310-targets
508 Bytes
execute_rom_ext_fpga_tests_cw310-test-results
8.03 KB
execute_rom_ext_fpga_tests_cw340-targets
234 Bytes
execute_rom_ext_fpga_tests_cw340-test-results
1.75 KB
execute_rom_fpga_tests_cw310-targets
1.8 KB
execute_rom_fpga_tests_cw310-test-results
47.4 KB
execute_rom_fpga_tests_cw340-targets
162 Bytes
execute_rom_fpga_tests_cw340-test-results
201 Bytes
execute_sival_fpga_tests_cw310-targets
784 Bytes
execute_sival_fpga_tests_cw310-test-results
37.4 KB
execute_sival_fpga_tests_cw340-targets
484 Bytes
execute_sival_fpga_tests_cw340-test-results
38.4 KB
execute_sival_rom_ext_fpga_tests_cw310-targets
2.2 KB
execute_sival_rom_ext_fpga_tests_cw310-test-results
179 KB
execute_sival_rom_ext_fpga_tests_cw340-targets
390 Bytes
execute_sival_rom_ext_fpga_tests_cw340-test-results
13.1 KB
execute_test_rom_fpga_tests_cw310-targets
346 Bytes
execute_test_rom_fpga_tests_cw310-test-results
7.24 KB
execute_test_rom_fpga_tests_cw340-targets
258 Bytes
execute_test_rom_fpga_tests_cw340-test-results
45.4 KB
partial-build-bin-chip_earlgrey_cw310
6.02 MB
partial-build-bin-chip_earlgrey_cw310_hyperdebug
6.05 MB
partial-build-bin-chip_earlgrey_cw340
9.81 MB
sw_build_test-test-results
60 KB
verilated_englishbreakfast
6.54 MB
verilator_earlgrey-test-results
8.9 KB