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[rtl] Readback mode and iCache MuBi encoding update #2170

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merged 5 commits into from
Jun 6, 2024
Merged

[rtl] Readback mode and iCache MuBi encoding update #2170

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8fd6e2e
[rtl] Update RAM ports inside ibex_top
nasahlpa May 28, 2024
6ad2233
[rtl] Add error port to iCache
nasahlpa May 28, 2024
5062b8a
Update lowrisc_ip to lowRISC/opentitan@d268f271f4
nasahlpa May 28, 2024
6960cbb
[dv] Add mubi and prim_count pkg to DV environment
nasahlpa May 28, 2024
fdcc7e8
[dv] Remove phase argument from collect_trans
nasahlpa May 28, 2024
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3 changes: 2 additions & 1 deletion dv/uvm/core_ibex/ibex_dv.f
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@
${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_pkg.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_assert.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_util_pkg.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_count_pkg.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_count.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_pkg.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_22_16_dec.sv
Expand All @@ -33,6 +34,7 @@
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_hamming_39_32_enc.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_hamming_72_64_dec.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_hamming_72_64_enc.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_mubi_pkg.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_ram_1p_pkg.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_ram_1p_adv.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_ram_1p_scr.sv
Expand Down Expand Up @@ -69,7 +71,6 @@
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_check.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_enc.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_mux.sv
${LOWRISC_IP_DIR}/ip/prim/rtl/prim_mubi_pkg.sv

// ibex CORE RTL files
+incdir+${PRJ_DIR}/rtl
Expand Down
2 changes: 1 addition & 1 deletion dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_monitor.sv
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Expand Up @@ -35,7 +35,7 @@ class ibex_icache_core_monitor extends dv_base_monitor #(
endtask

// collect transactions forever - already forked in dv_base_moditor::run_phase
virtual protected task collect_trans(uvm_phase phase);
virtual protected task collect_trans();
ibex_icache_core_bus_item trans;
logic last_inval = 0;
logic last_enable = 0;
Expand Down
2 changes: 1 addition & 1 deletion dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_monitor.sv
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Expand Up @@ -30,7 +30,7 @@ class ibex_icache_mem_monitor
endtask

// Collect transactions forever. Forked in dv_base_moditor::run_phase
protected task automatic collect_trans(uvm_phase phase);
protected task automatic collect_trans();
fork
collect_grants();
collect_responses();
Expand Down
90 changes: 48 additions & 42 deletions dv/uvm/icache/dv/tb/tb.sv
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Expand Up @@ -138,27 +138,30 @@ module tb #(
.EnableParity (0),
.NumAddrScrRounds (NumAddrScrRounds)
) tag_bank (
.clk_i (clk),
.rst_ni (rst_n),

.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),

.req_i (ram_if.ic_tag_req[way]),

.gnt_o (),
.write_i (ram_if.ic_tag_write),
.addr_i (ram_if.ic_tag_addr),
.wdata_i (ram_if.ic_tag_wdata),
.wmask_i ({TagSizeECC{1'b1}}),
.intg_error_i(1'b0),

.rdata_o (ram_if.ic_tag_rdata_in[way]),
.rvalid_o (ram_if.ic_tag_rvalid[way]),
.raddr_o (),
.rerror_o (),
.cfg_i ('0)
.clk_i (clk),
.rst_ni (rst_n),

.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),

.req_i (ram_if.ic_tag_req[way]),

.gnt_o (),
.write_i (ram_if.ic_tag_write),
.addr_i (ram_if.ic_tag_addr),
.wdata_i (ram_if.ic_tag_wdata),
.wmask_i ({TagSizeECC{1'b1}}),
.intg_error_i (1'b0),

.rdata_o (ram_if.ic_tag_rdata_in[way]),
.rvalid_o (ram_if.ic_tag_rvalid[way]),
.raddr_o (),
.rerror_o (),
.cfg_i ('0),
.wr_collision_o (),
.write_pending_o (),
.alert_o ()
);

// Data RAM instantiation
Expand All @@ -170,27 +173,30 @@ module tb #(
.ReplicateKeyStream (1),
.NumAddrScrRounds (NumAddrScrRounds)
) data_bank (
.clk_i (clk),
.rst_ni (rst_n),

.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),

.req_i (ram_if.ic_data_req[way]),

.gnt_o (),
.write_i (ram_if.ic_data_write),
.addr_i (ram_if.ic_data_addr),
.wdata_i (ram_if.ic_data_wdata),
.wmask_i ({LineSizeECC{1'b1}}),
.intg_error_i(1'b0),

.rdata_o (ram_if.ic_data_rdata_in[way]),
.rvalid_o (ram_if.ic_data_rvalid[way]),
.raddr_o (),
.rerror_o (),
.cfg_i ('0)
.clk_i (clk),
.rst_ni (rst_n),

.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),

.req_i (ram_if.ic_data_req[way]),

.gnt_o (),
.write_i (ram_if.ic_data_write),
.addr_i (ram_if.ic_data_addr),
.wdata_i (ram_if.ic_data_wdata),
.wmask_i ({LineSizeECC{1'b1}}),
.intg_error_i (1'b0),

.rdata_o (ram_if.ic_data_rdata_in[way]),
.rvalid_o (ram_if.ic_data_rvalid[way]),
.raddr_o (),
.rerror_o (),
.cfg_i ('0),
.wr_collision_o (),
.write_pending_o (),
.alert_o ()
);
end

Expand Down
1 change: 1 addition & 0 deletions ibex_core.core
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Expand Up @@ -11,6 +11,7 @@ filesets:
- lowrisc:prim:assert
- lowrisc:prim:clock_gating
- lowrisc:prim:lfsr
- lowrisc:prim:mubi
- lowrisc:ibex:ibex_pkg
- lowrisc:ibex:ibex_icache
- lowrisc:dv:dv_fcov_macros
Expand Down
83 changes: 52 additions & 31 deletions rtl/ibex_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -552,6 +552,9 @@ module ibex_top import ibex_pkg::*; #(
// Rams Instantiation //
////////////////////////

logic [IC_NUM_WAYS-1:0] icache_tag_alert;
logic [IC_NUM_WAYS-1:0] icache_data_alert;

if (ICache) begin : gen_rams

for (genvar way = 0; way < IC_NUM_WAYS; way++) begin : gen_rams_inner
Expand All @@ -571,24 +574,28 @@ module ibex_top import ibex_pkg::*; #(
.clk_i,
.rst_ni,

.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),
.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),

.req_i (ic_tag_req[way]),
.req_i (ic_tag_req[way]),

.gnt_o (),
.write_i (ic_tag_write),
.addr_i (ic_tag_addr),
.wdata_i (ic_tag_wdata),
.wmask_i ({TagSizeECC{1'b1}}),
.intg_error_i(1'b0),
.gnt_o (),
.write_i (ic_tag_write),
.addr_i (ic_tag_addr),
.wdata_i (ic_tag_wdata),
.wmask_i ({TagSizeECC{1'b1}}),
.intg_error_i (1'b0),

.rdata_o (ic_tag_rdata[way]),
.rvalid_o (),
.raddr_o (),
.rerror_o (),
.cfg_i (ram_cfg_i)
.rdata_o (ic_tag_rdata[way]),
.rvalid_o (),
.raddr_o (),
.rerror_o (),
.cfg_i (ram_cfg_i),
.wr_collision_o (),
.write_pending_o (),

.alert_o (icache_tag_alert[way])
);

// Data RAM instantiation
Expand All @@ -604,24 +611,28 @@ module ibex_top import ibex_pkg::*; #(
.clk_i,
.rst_ni,

.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),
.key_valid_i (scramble_key_valid_q),
.key_i (scramble_key_q),
.nonce_i (scramble_nonce_q),

.req_i (ic_data_req[way]),
.req_i (ic_data_req[way]),

.gnt_o (),
.write_i (ic_data_write),
.addr_i (ic_data_addr),
.wdata_i (ic_data_wdata),
.wmask_i ({LineSizeECC{1'b1}}),
.intg_error_i(1'b0),
.gnt_o (),
.write_i (ic_data_write),
.addr_i (ic_data_addr),
.wdata_i (ic_data_wdata),
.wmask_i ({LineSizeECC{1'b1}}),
.intg_error_i (1'b0),

.rdata_o (ic_data_rdata[way]),
.rvalid_o (),
.raddr_o (),
.rerror_o (),
.cfg_i (ram_cfg_i)
.rdata_o (ic_data_rdata[way]),
.rvalid_o (),
.raddr_o (),
.rerror_o (),
.cfg_i (ram_cfg_i),
.wr_collision_o (),
.write_pending_o (),

.alert_o (icache_data_alert[way])
);

`ifdef INC_ASSERT
Expand Down Expand Up @@ -694,6 +705,8 @@ module ibex_top import ibex_pkg::*; #(
.cfg_i (ram_cfg_i)
);

assign icache_tag_alert = '{default:'b0};
assign icache_data_alert = '{default:'b0};
end
end

Expand All @@ -712,6 +725,8 @@ module ibex_top import ibex_pkg::*; #(
assign ic_tag_rdata = '{default:'b0};
assign ic_data_rdata = '{default:'b0};

assign icache_tag_alert = '{default:'b0};
assign icache_data_alert = '{default:'b0};
end

assign data_wdata_o = data_wdata_core[31:0];
Expand Down Expand Up @@ -1082,9 +1097,15 @@ module ibex_top import ibex_pkg::*; #(
assign unused_scan = scan_rst_ni;
end

// Enable or disable iCache multi bit encoding checking error generation.
// If enabled and a MuBi encoding error is detected, raise a major alert.
logic icache_alert_major_internal;
assign icache_alert_major_internal = (|icache_tag_alert) | (|icache_data_alert);

assign alert_major_internal_o = core_alert_major_internal |
lockstep_alert_major_internal |
rf_alert_major_internal;
rf_alert_major_internal |
icache_alert_major_internal;
assign alert_major_bus_o = core_alert_major_bus | lockstep_alert_major_bus;
assign alert_minor_o = core_alert_minor | lockstep_alert_minor;

Expand Down
4 changes: 2 additions & 2 deletions vendor/lowrisc_ip.lock.hjson
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@@ -1,4 +1,4 @@
// Copyright lowRISC contributors.
// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

Expand All @@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/lowRISC/opentitan
rev: e0c40265019aa0c74e6903d3b3a144c48a3815ec
rev: d268f271f4f75aeb8f3bf9624a497ae5bfb9c47e
}
}
2 changes: 1 addition & 1 deletion vendor/lowrisc_ip/dv/sv/common_ifs/clk_if.sv
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@@ -1,4 +1,4 @@
// Copyright lowRISC contributors.
// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

Expand Down
4 changes: 3 additions & 1 deletion vendor/lowrisc_ip/dv/sv/common_ifs/clk_rst_if.sv
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@@ -1,4 +1,4 @@
// Copyright lowRISC contributors.
// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

Expand Down Expand Up @@ -136,13 +136,15 @@ interface clk_rst_if #(

// set the clk frequency in khz
function automatic void set_freq_khz(int freq_khz);
`DV_CHECK_FATAL(freq_khz > 0, , msg_id)
clk_freq_mhz = $itor(freq_khz) / 1000;
clk_period_ps = 1000_000 / clk_freq_mhz;
recompute = 1'b1;
endfunction

// set the clk frequency in mhz
function automatic void set_freq_mhz(int freq_mhz);
`DV_CHECK_FATAL(freq_mhz > 0, , msg_id)
set_freq_khz(freq_mhz * 1000);
endfunction

Expand Down
2 changes: 1 addition & 1 deletion vendor/lowrisc_ip/dv/sv/common_ifs/common_ifs.core
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@@ -1,5 +1,5 @@
CAPI=2:
# Copyright lowRISC contributors.
# Copyright lowRISC contributors (OpenTitan project).
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:dv:common_ifs"
Expand Down
2 changes: 1 addition & 1 deletion vendor/lowrisc_ip/dv/sv/common_ifs/common_ifs_pkg.sv
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@@ -1,4 +1,4 @@
// Copyright lowRISC contributors.
// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

Expand Down
2 changes: 1 addition & 1 deletion vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_if.core
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@@ -1,5 +1,5 @@
CAPI=2:
# Copyright lowRISC contributors.
# Copyright lowRISC contributors (OpenTitan project).
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:dv:entropy_subsys_fifo_exception_if"
Expand Down
2 changes: 1 addition & 1 deletion vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_if.sv
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@@ -1,4 +1,4 @@
// Copyright lowRISC contributors.
// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
Expand Down
2 changes: 1 addition & 1 deletion vendor/lowrisc_ip/dv/sv/common_ifs/entropy_subsys_fifo_exception_pkg.sv
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@@ -1,4 +1,4 @@
// Copyright lowRISC contributors.
// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

Expand Down
2 changes: 1 addition & 1 deletion vendor/lowrisc_ip/dv/sv/common_ifs/pins_if.sv
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@@ -1,4 +1,4 @@
// Copyright lowRISC contributors.
// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

Expand Down
2 changes: 1 addition & 1 deletion vendor/lowrisc_ip/dv/sv/common_ifs/pins_ifs.core
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@@ -1,5 +1,5 @@
CAPI=2:
# Copyright lowRISC contributors.
# Copyright lowRISC contributors (OpenTitan project).
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:dv:pins_if"
Expand Down
2 changes: 1 addition & 1 deletion vendor/lowrisc_ip/dv/sv/common_ifs/rst_shadowed_if.core
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@@ -1,5 +1,5 @@
CAPI=2:
# Copyright lowRISC contributors.
# Copyright lowRISC contributors (OpenTitan project).
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:dv:rst_shadowed_if"
Expand Down
2 changes: 1 addition & 1 deletion vendor/lowrisc_ip/dv/sv/common_ifs/rst_shadowed_if.sv
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@@ -1,4 +1,4 @@
// Copyright lowRISC contributors.
// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

Expand Down
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