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[rtl] Move counter_q definition
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The counter_q definition should be outside of the if else such that
we have the correct scope. Moreover, Xilinx Vivado reports an
error if the DspPragma is a string instead of an int. Finally,
Xilinx complained that COUNTER_FLOP_RST is redefined.

Signed-off-by: Pascal Nasahl <[email protected]>
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nasahlpa committed Dec 2, 2024
1 parent 54985d2 commit d92213a
Showing 1 changed file with 31 additions and 18 deletions.
49 changes: 31 additions & 18 deletions rtl/ibex_counter.sv
Original file line number Diff line number Diff line change
Expand Up @@ -50,33 +50,46 @@ module ibex_counter #(
end
end

`define ASYNC_RST_FF(CLK, RST_NI, Q, D) \
always_ff @(posedge CLK or negedge RST_NI) begin \
if (!RST_NI) begin \
Q <= '0; \
end else begin \
Q <= D; \
end \
end

`define SYNC_RST_FF(CLK, RST_NI, Q, D) \
always_ff @(posedge CLK) begin \
if (!RST_NI) begin \
Q <= '0; \
end else begin \
Q <= D; \
end \
end

`ifdef FPGA_XILINX
// On Xilinx FPGAs, 48-bit DSPs are available that can be used for the
// counter.
if (CounterWidth < 49) begin : g_dsp_counter
// Set DSP pragma for supported xilinx FPGAs
(* use_dsp = "yes" *) logic [CounterWidth-1:0] counter_q;
// DSP output register requires synchronous reset.
`define COUNTER_FLOP_RST posedge clk_i
end else begin : g_no_dsp_counter
(* use_dsp = "no" *) logic [CounterWidth-1:0] counter_q;
`define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni
end
localparam int DspPragma = CounterWidth < 49 ? "yes" : "no";
(* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q;
// When using a DSP, a synchronous reset is needed.
localparam string ResetType = CounterWidth < 49 ? "SYNC" : "ASYNC";
`else
logic [CounterWidth-1:0] counter_q;

`define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni
localparam string ResetType = "ASYNC";
`endif

// Counter flop
always_ff @(`COUNTER_FLOP_RST) begin
`undef COUNTER_FLOP_RST
if (!rst_ni) begin
counter_q <= '0;
end else begin
counter_q <= counter_d;
generate
if(ResetType == "ASYNC") begin : g_async_reset_ff
`ASYNC_RST_FF(clk_i, rst_ni, counter_q, counter_d);
`undef ASYNC_RST_FF
end else begin : g_sync_reset_ff
`SYNC_RST_FF(clk_i, rst_ni, counter_q, counter_d);
`undef SYNC_RST_FF
end
end
endgenerate

if (CounterWidth < 64) begin : g_counter_narrow
logic [63:CounterWidth] unused_counter_load;
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