-
Notifications
You must be signed in to change notification settings - Fork 554
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Update google_riscv-dv to chipsalliance/riscv-dv@71666eb
Update code from upstream repository https://github.com/chipsalliance/riscv-dv to revision 71666ebacd69266b1abb7cdbad5e1897ce5884e6 * Fixes to support RV32 (Maciej Kurc) * Extend CI matrix (Eryk Szpotanski) * Add pyflow test (Grzegorz Placzek) * Allow the CI to run from any branch and any PR (Maciej Kurc) * [pmp] Remove MSECCFG reads from trap handler when Smepmp is disabled (Marno van der Maas) Signed-off-by: Greg Chadwick <[email protected]>
- Loading branch information
Showing
14 changed files
with
431 additions
and
58 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,106 @@ | ||
#!/usr/bin/env python3 | ||
import argparse | ||
import re | ||
|
||
# ============================================================================= | ||
|
||
class AssemblyLine: | ||
""" | ||
Simple assembly line representation | ||
""" | ||
|
||
RE_INSTR = re.compile(r"(?P<mnemonic>\S+)\s+(?P<operands>.*)") | ||
|
||
def __init__(self, text): | ||
self.text = text | ||
self.mnemonic = None | ||
self.operands = None | ||
|
||
# Strip label if any | ||
if ":" in text: | ||
text = text.split(":", maxsplit=1)[1] | ||
|
||
# Strip comment if any | ||
if "#" in text: | ||
text = text.split("#", maxsplit=1)[0] | ||
|
||
# Get instruction and operands | ||
m = self.RE_INSTR.match(text.strip()) | ||
if m is not None: | ||
|
||
if m.group("mnemonic")[0] == ".": | ||
return | ||
|
||
self.mnemonic = m.group("mnemonic").lower() | ||
self.operands = [op.strip() for op in m.group("operands").split()] | ||
|
||
def __str__(self): | ||
return self.text | ||
|
||
# ============================================================================= | ||
|
||
|
||
def main(): | ||
parser = argparse.ArgumentParser() | ||
parser.add_argument( | ||
"-i", | ||
type=str, | ||
required=True, | ||
help="Input assembly file" | ||
) | ||
parser.add_argument( | ||
"-o", | ||
type=str, | ||
required=True, | ||
help="Output assembly file" | ||
) | ||
|
||
args = parser.parse_args() | ||
|
||
max_nops = 10 | ||
|
||
# Read and parse | ||
with open(args.i, "r") as fp: | ||
inp_lines = [AssemblyLine(l) for l in fp.readlines()] | ||
|
||
# Identify a delayed write instruction followed by another one which writes | ||
# to the same register | ||
out_lines = [] | ||
for i in range(len(inp_lines)): | ||
line = inp_lines[i] | ||
out_lines.append(line) | ||
|
||
# Bypass | ||
if not line.mnemonic: | ||
continue | ||
|
||
# Check if it is a delayed write. If not then bypass | ||
is_delayed = line.mnemonic in ["div", "divu", "rem", "remu", "lw"] | ||
if not is_delayed: | ||
continue | ||
|
||
# Get next 2 instructions | ||
following = [] | ||
for j in range(i+1, len(inp_lines)): | ||
if inp_lines[j].mnemonic is not None: | ||
following.append(inp_lines[j]) | ||
if len(following) >= 2: | ||
break | ||
|
||
# If any of the instructions targets the same register insert NOPs | ||
dst = line.operands[0] | ||
for j, l in enumerate(following): | ||
if l.operands and l.operands[0] == dst: | ||
nops = max(0, max_nops - j) | ||
for _ in range(nops): | ||
out_lines.append(" " * 18 + "nop # FIXME: A fixup not to make VeeR cancel a delayed write\n") | ||
break | ||
|
||
# Write | ||
with open(args.o, "w") as fp: | ||
for l in out_lines: | ||
fp.write(str(l)) | ||
|
||
|
||
if __name__ == "__main__": | ||
main() |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,26 @@ | ||
import sys | ||
from json import dumps | ||
from yaml import load, Loader | ||
from typing import Generator | ||
|
||
|
||
def parse_yaml(path: str) -> Generator[str, None, None]: | ||
with open(path, 'rb') as fd: | ||
tests = load(fd, Loader=Loader) | ||
for test in tests: | ||
if 'import' in test: | ||
import_path = test['import'].split('/', 1)[1] | ||
yield from parse_yaml(import_path) | ||
elif 'test' in test: | ||
yield test['test'] | ||
|
||
|
||
if __name__ == "__main__": | ||
if len(sys.argv) == 2: | ||
testlist = parse_yaml(f'target/{sys.argv[1]}/testlist.yaml') | ||
else: | ||
testlist = parse_yaml('yaml/base_testlist.yaml') | ||
testlist = list(testlist) | ||
# remove, will cause incomplete sim, need customized RTL | ||
testlist.remove("riscv_csr_test") | ||
print(dumps(testlist)) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,63 @@ | ||
# https://github.com/chipsalliance/Cores-VeeR-EL2/blob/774510e43f5408ec2b818db8f865027bc9be97b8/.github/workflows/build-spike.yml | ||
|
||
name: Spike Build | ||
|
||
on: | ||
workflow_call: | ||
|
||
jobs: | ||
verilator: | ||
name: Build Spike | ||
runs-on: ubuntu-latest | ||
env: | ||
TOOL_NAME: spike | ||
TOOL_VERSION: d70ea67d | ||
DEBIAN_FRONTEND: "noninteractive" | ||
|
||
steps: | ||
- name: Setup Cache Metadata | ||
id: cache_metadata | ||
run: | | ||
cache_date=$(date +"%Y_%m_%d") | ||
cache_name=cache_${{ env.TOOL_NAME }}_${{ env.TOOL_VERSION }} | ||
echo "Cache date: "$cache_date | ||
echo "Cache name: "$cache_name | ||
echo "cache_date=$cache_date" >> "$GITHUB_ENV" | ||
echo "cache_name=$cache_name" >> "$GITHUB_ENV" | ||
- name: Setup cache | ||
uses: actions/cache@v3 | ||
id: cache | ||
timeout-minutes: 60 | ||
with: | ||
path: | | ||
/opt/spike | ||
/opt/spike/.cache | ||
key: ${{ env.cache_name }}_${{ env.cache_date }} | ||
restore-keys: ${{ env.cache_name }}_ | ||
|
||
- name: Install prerequisities | ||
if: ${{ steps.cache.outputs.cache-hit != 'true' }} | ||
run: | | ||
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ | ||
git build-essential cmake ccache device-tree-compiler | ||
- name: Build Spike | ||
if: ${{ steps.cache.outputs.cache-hit != 'true' }} | ||
run: | | ||
export CCACHE_DIR=/opt/spike/.cache | ||
ccache --show-config | grep cache_dir | ||
git clone https://github.com/riscv-software-src/riscv-isa-sim spike | ||
export CC="ccache gcc" | ||
export CXX="ccache g++" | ||
pushd spike | ||
git checkout ${{ env.TOOL_VERSION }} | ||
mkdir build | ||
cd build | ||
../configure --prefix=/opt/spike | ||
make -j`nproc` | ||
make install | ||
popd | ||
rm -rf /opt/spike/include # Remove include and lib to save space | ||
rm -rf /opt/spike/lib | ||
27 changes: 0 additions & 27 deletions
27
vendor/google_riscv-dv/.github/workflows/metrics-regress.yml
This file was deleted.
Oops, something went wrong.
Oops, something went wrong.