[rtl] Add error port to iCache

This commit adds the error port to the iCache which was introduced with lowRISC/opentitan#23292. Signed-off-by: Pascal Nasahl <[email protected]>
lowRISC · May 28, 2024 · 50322d4 · 50322d4
1 parent 6eacc30
commit 50322d4
Show file tree

Hide file tree

Showing 3 changed files with 25 additions and 6 deletions.
diff --git a/dv/uvm/core_ibex/ibex_dv.f b/dv/uvm/core_ibex/ibex_dv.f
@@ -33,6 +33,7 @@
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_hamming_39_32_enc.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_hamming_72_64_dec.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_secded_hamming_72_64_enc.sv
+${LOWRISC_IP_DIR}/ip/prim/rtl/prim_mubi_pkg.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_ram_1p_pkg.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_ram_1p_adv.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_ram_1p_scr.sv
@@ -69,7 +70,6 @@
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_check.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_enc.sv
 ${LOWRISC_IP_DIR}/ip/prim/rtl/prim_onehot_mux.sv
-${LOWRISC_IP_DIR}/ip/prim/rtl/prim_mubi_pkg.sv
 
 // ibex CORE RTL files
 +incdir+${PRJ_DIR}/rtl

diff --git a/dv/uvm/icache/dv/tb/tb.sv b/dv/uvm/icache/dv/tb/tb.sv
@@ -160,7 +160,8 @@ module tb #(
       .rerror_o         (),
       .cfg_i            ('0),
       .wr_collision_o   (),
-      .write_pending_o  ()
+      .write_pending_o  (),
+      .alert_o          ()
     );
 
     // Data RAM instantiation
@@ -194,7 +195,8 @@ module tb #(
       .rerror_o         (),
       .cfg_i            ('0),
       .wr_collision_o   (),
-      .write_pending_o  ()
+      .write_pending_o  (),
+      .alert_o          ()
     );
   end
 

diff --git a/rtl/ibex_top.sv b/rtl/ibex_top.sv
@@ -552,6 +552,9 @@ module ibex_top import ibex_pkg::*; #(
   // Rams Instantiation //
   ////////////////////////
 
+  logic [IC_NUM_WAYS-1:0] icache_tag_alert;
+  logic [IC_NUM_WAYS-1:0] icache_data_alert;
+
   if (ICache) begin : gen_rams
 
     for (genvar way = 0; way < IC_NUM_WAYS; way++) begin : gen_rams_inner
@@ -590,7 +593,9 @@ module ibex_top import ibex_pkg::*; #(
           .rerror_o         (),
           .cfg_i            (ram_cfg_i),
           .wr_collision_o   (),
-          .write_pending_o  ()
+          .write_pending_o  (),
+
+          .alert_o          (icache_tag_alert[way])
         );
 
         // Data RAM instantiation
@@ -625,7 +630,9 @@ module ibex_top import ibex_pkg::*; #(
           .rerror_o         (),
           .cfg_i            (ram_cfg_i),
           .wr_collision_o   (),
-          .write_pending_o  ()
+          .write_pending_o  (),
+
+          .alert_o          (icache_data_alert[way])
         );
 
         `ifdef INC_ASSERT
@@ -698,6 +705,8 @@ module ibex_top import ibex_pkg::*; #(
           .cfg_i       (ram_cfg_i)
         );
 
+        assign icache_tag_alert  = '{default:'b0};
+        assign icache_data_alert = '{default:'b0};
       end
     end
 
@@ -716,6 +725,8 @@ module ibex_top import ibex_pkg::*; #(
     assign ic_tag_rdata      = '{default:'b0};
     assign ic_data_rdata     = '{default:'b0};
 
+    assign icache_tag_alert  = '{default:'b0};
+    assign icache_data_alert = '{default:'b0};
   end
 
   assign data_wdata_o = data_wdata_core[31:0];
@@ -1086,9 +1097,15 @@ module ibex_top import ibex_pkg::*; #(
     assign unused_scan = scan_rst_ni;
   end
 
+  // Enable or disable iCache multi bit encoding checking error generation.
+  // If enabled and a MuBi encoding error is detected, raise a major alert.
+  logic icache_alert_major_internal;
+  assign icache_alert_major_internal = (|icache_tag_alert) | (|icache_data_alert);
+
   assign alert_major_internal_o = core_alert_major_internal |
                                   lockstep_alert_major_internal |
-                                  rf_alert_major_internal;
+                                  rf_alert_major_internal |
+                                  icache_alert_major_internal;
   assign alert_major_bus_o      = core_alert_major_bus | lockstep_alert_major_bus;
   assign alert_minor_o          = core_alert_minor | lockstep_alert_minor;