[dv] Add spurious responses to memory agent #176
Annotations
1 error and 4 warnings
|
dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L165
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:165 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
|
dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L166
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:166 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
|
dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L167
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:167 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
|
dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L170
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 156 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 156 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:170 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
|
This job failed
Loading