[dv] Add riscv_rf_ctrl_intg_test #165
Annotations
1 error and 2 warnings
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dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L164
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 154 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 154 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:164 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L165
[verible-verilog-lint] reported by reviewdog 🐶
Line length exceeds max: 100; is: 154 [Style: line-length] [line-length]
Raw Output:
message:"Line length exceeds max: 100; is: 154 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:165 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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