[rtl,pmp] Allow all accesses to Debug Module in debug mode #257
andreaskurthci.yml
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The RISC-V compliance test suite failed for rv32i
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Expected failure for rv32i, see lowrisc/ibex#100 more more information.
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Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint --tool=verilator lowrisc:ibex:ibex_top_tracing --RV32E=0 --RV32M=ibex_pkg::RV32MSingleCycle --RV32B=ibex_pkg::RV32BOTEarlGrey --RegFile=ibex_pkg::RegFileFF --BranchTargetALU=1 --WritebackStage=1 --ICache=1 --ICacheECC=1 --ICacheScramble=1 --BranchPredictor=0 --DbgTriggerEn=1 --SecureIbex=1 --PMPEnable=1 --PMPGranularity=0 --PMPNumRegions=16 --MHPMCounterNum=10 --MHPMCounterWidth=32' to check and fix all errors.
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Process completed with exit code 1.
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