Skip to content
pr-lint

[rtl] Fix counter reset value on FPGA #241

Sign in to view logs

[rtl] Fix counter reset value on FPGA

[rtl] Fix counter reset value on FPGA #241

Triggered via pull request November 28, 2024 06:52
@nasahlpanasahlpa
synchronize #2226
nasahlpa:fix_counter_reset_value
Status Success
Total duration 51s
Artifacts 1

pr_lint.yml

on: pull_request
verible-lint
41s
verible-lint
Fit to window
Zoom out
Zoom in

Artifacts

Produced during runtime
Name Size
verible-linter
2.47 KB