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Configurable UART #57

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Configurable UART #57

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cb47213
[rtl] removed original uart.sv file and added my uart implementation …
AgamemnonasKyriazis Jul 18, 2023
66d920b
[core] edited the .core files to include my verilog file to compile p…
AgamemnonasKyriazis Jul 18, 2023
7d9ad09
[sw] edited common header files to support configurable uart paramete…
AgamemnonasKyriazis Jul 18, 2023
b6ee853
[sw c]Deleted link.ld, it was a copy mistake and it shouldn't be ther…
AgamemnonasKyriazis Jul 18, 2023
0850f84
almost full and almost empty condition flags
AgamemnonasKyriazis Sep 30, 2023
7807f35
bugfix
AgamemnonasKyriazis Sep 30, 2023
9eca9d0
Update main.c
AgamemnonasKyriazis Oct 5, 2023
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3 changes: 1 addition & 2 deletions ibex_demo_system.core
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Original file line number Diff line number Diff line change
Expand Up @@ -107,8 +107,7 @@ targets:
toplevel: top_cw305
tools:
vivado:
part: "xc7a100tftg256-2" # default to a100 part
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#part: "xc7a35tftg256-2" # a35 option
part: "xc7a35tftg256-2" # a35 option
parameters:
- SRAMInitFile
- PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
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8 changes: 7 additions & 1 deletion ibex_demo_system_core.core
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Expand Up @@ -16,7 +16,13 @@ filesets:
- rtl/system/gpio.sv
- rtl/system/pwm.sv
- rtl/system/pwm_wrapper.sv
- rtl/system/uart.sv
- rtl/system/uart_top.v
- rtl/system/uart_rx.v
- rtl/system/uart_tx.v
- rtl/system/sync_fifo.v
- rtl/system/async_fifo.v
- rtl/system/uart.vh
- rtl/system/synchronizer.v
- rtl/system/spi_host.sv
- rtl/system/spi_top.sv
file_type: systemVerilogSource
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