Update feature list

lowRISC · Oct 12, 2023 · 49996e6 · 49996e6
1 parent 9987dd9
commit 49996e6
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/README.md b/README.md
@@ -7,8 +7,8 @@ This an example RISC-V SoC targeting the Arty-A7 FPGA board. It comprises the
 following features:
 
 * RISC-V debug support (using the [PULP RISC-V Debug Module](https://github.com/pulp-platform/riscv-dbg))
-* A UART
-* GPIO (output only for now)
+* UART
+* GPIO
 * Timer
 * SPI
 * A basic peripheral to write ASCII output to a file and halt simulation from software