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PV Attributes and other fixes #19

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merged 6 commits into from
Aug 31, 2023
Merged

PV Attributes and other fixes #19

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2466d53
timingApp: add PINI to DevEnbl-Sel records.
ericonr Aug 22, 2023
36e8169
timingApp: remove unused records from evg.db.
ericonr Aug 22, 2023
f8cf873
timingApp: add EGU to FPGAClk-Cte.
ericonr Aug 22, 2023
dbbcfe2
timingApp: update FPGAClk-Cte.INP.
ericonr Aug 22, 2023
5b52ee3
timingApp: add PINI to OTP State-Sel.
ericonr Aug 24, 2023
8553f7d
timingApp: add PINI to IntlkCtrlEnbl-Sel.
ericonr Aug 24, 2023
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4 changes: 3 additions & 1 deletion timingApp/Db/eve.db
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Original file line number Diff line number Diff line change
Expand Up @@ -3,10 +3,11 @@

record(ai, "$(P)$(R)FPGAClk-Cte") {
field(DESC, "FPGA Clock from EVG")
field(EGU, "Hz")
field(SCAN, "1 second")
field(PINI, "1")
field(VAL, "124914500")
field(INP, "RA-RaMO:TI-EVG:FPGAClk-Cte")
field(INP, "AS-RaMO:TI-EVG:FPGAClk-Cte")
}

record(stringout, "$(P)$(R)IPAddr-Mon"){
Expand All @@ -29,6 +30,7 @@ record(bo, "$(P)$(R)DevEnbl-Sel") {
field(ZNAM, "Dsbl")
field(ONAM, "Enbl")
field(OUT, "@timing.proto evre_ctrl_set($(P),$(R)) $(PORT)")
field(PINI, YES)
}

record(mbbiDirect, "$(P)$(R)DevEnblRaw") {
Expand Down
11 changes: 2 additions & 9 deletions timingApp/Db/evg.db
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Original file line number Diff line number Diff line change
Expand Up @@ -191,6 +191,7 @@ record(bo, "$(P)$(R)DevEnbl-Sel"){
field(ZNAM, "Dsbl")
field(ONAM, "Enbl")
field(FLNK, "$(P)$(R)EVGEN")
field(PINI, YES)
}

record(longout, "$(P)$(R)cmd_ctrl_get") {
Expand Down Expand Up @@ -766,15 +767,6 @@ record(longout, "$(P)$(R)cmd_diginp_get1") {
########################################################################
# Interlock map [56]

record(mbboDirect, "$(P)$(R)ilock_mbbo") {
field(DESC, "interlock input to output map")
}

record(mbbiDirect, "$(P)$(R)ilock_mbbi") {
field(DESC, "interlock input to output map")
field(VAL, "1")
}

record(seq, "$(P)$(R)ilock_seq1") {
field(DESC, "interlock input to output map")
field(DOL1, "$(P)$(R)IntlkTbl0to15-Sts.B0")
Expand Down Expand Up @@ -1019,6 +1011,7 @@ record(bo, "$(P)$(R)IntlkCtrlEnbl-Sel") {
field(ZNAM, "Dsbl")
field(ONAM, "Enbl")
field(FLNK, "$(P)$(R)IntlkCtrlEnblCalc")
field(PINI, YES)
}

record(bo, "$(P)$(R)IntlkCtrlRst-Sel") {
Expand Down
4 changes: 3 additions & 1 deletion timingApp/Db/evr.db
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Original file line number Diff line number Diff line change
Expand Up @@ -3,10 +3,11 @@

record(ai, "$(P)$(R)FPGAClk-Cte") {
field(DESC, "FPGA Clock from EVG")
field(EGU, "Hz")
field(SCAN, "1 second")
field(PINI, "1")
field(VAL, "124914500")
field(INP, "RA-RaMO:TI-EVG:FPGAClk-Cte")
field(INP, "AS-RaMO:TI-EVG:FPGAClk-Cte")
}

record(stringout, "$(P)$(R)IPAddr-Mon"){
Expand All @@ -29,6 +30,7 @@ record(bo, "$(P)$(R)DevEnbl-Sel") {
field(ZNAM, "Dsbl")
field(ONAM, "Enbl")
field(OUT, "@timing.proto evre_ctrl_set($(P),$(R)) $(PORT)")
field(PINI, YES)
}

record(mbbiDirect, "$(P)$(R)DevEnblRaw") {
Expand Down
1 change: 1 addition & 0 deletions timingApp/Db/evre_otp.db
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Original file line number Diff line number Diff line change
Expand Up @@ -97,6 +97,7 @@ record(bo, "$(P)$(R)OTP$(num)State-Sel") {
field(ZNAM, "Dsbl")
field(ONAM, "Enbl")
field(FLNK, "$(P)$(R)OTP$(num)RegAByte3")
field(PINI, YES)
}

record(bo, "$(P)$(R)OTP$(num)Polarity-Sel") {
Expand Down
1 change: 1 addition & 0 deletions timingApp/Db/fout.db
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Original file line number Diff line number Diff line change
Expand Up @@ -75,6 +75,7 @@ record(bo, "$(P)$(R)DevEnbl-Sel"){
field(ZNAM, "Dsbl")
field(ONAM, "Enbl")
field(OUT, "@timing.proto fout_ctrl_set($(P),$(R)) $(PORT)")
field(PINI, YES)
}

record(longout, "$(P)$(R)cmd_ctrl_get") {
Expand Down