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wb_orbit_intlk testbench re-written in VHDL, bug fixes
To avoid depending on proprietary (and expensive) mixed-language HDL simulators, migrate the orbit interlock testbench to VHDL, add support for NVC and GHDL. All tests: Clear interlock latches before testing the interlock condition. Test 7: The orbit_intlk_trans_min_x/y thresholds were set to 0, but the decimated position was negative, causing an interlock condition.
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
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package wb_orbit_intlk_regs_const_pkg is | ||
constant ADDR_ORBIT_INTLK_CTRL : std_logic_vector(31 downto 0) := x"00000000"; | ||
constant ORBIT_INTLK_CTRL_EN_OFFSET : integer := 0; | ||
constant ORBIT_INTLK_CTRL_EN : std_logic_vector(31 downto 0) := x"00000001"; | ||
constant ORBIT_INTLK_CTRL_CLR_OFFSET : integer := 1; | ||
constant ORBIT_INTLK_CTRL_CLR : std_logic_vector(31 downto 0) := x"00000002"; | ||
constant ORBIT_INTLK_CTRL_MIN_SUM_EN_OFFSET : integer := 2; | ||
constant ORBIT_INTLK_CTRL_MIN_SUM_EN : std_logic_vector(31 downto 0) := x"00000004"; | ||
constant ORBIT_INTLK_CTRL_TRANS_EN_OFFSET : integer := 3; | ||
constant ORBIT_INTLK_CTRL_TRANS_EN : std_logic_vector(31 downto 0) := x"00000008"; | ||
constant ORBIT_INTLK_CTRL_TRANS_CLR_OFFSET : integer := 4; | ||
constant ORBIT_INTLK_CTRL_TRANS_CLR : std_logic_vector(31 downto 0) := x"00000010"; | ||
constant ORBIT_INTLK_CTRL_ANG_EN_OFFSET : integer := 5; | ||
constant ORBIT_INTLK_CTRL_ANG_EN : std_logic_vector(31 downto 0) := x"00000020"; | ||
constant ORBIT_INTLK_CTRL_ANG_CLR_OFFSET : integer := 6; | ||
constant ORBIT_INTLK_CTRL_ANG_CLR : std_logic_vector(31 downto 0) := x"00000040"; | ||
constant ORBIT_INTLK_CTRL_RESERVED_OFFSET : integer := 7; | ||
constant ORBIT_INTLK_CTRL_RESERVED : std_logic_vector(31 downto 0) := x"7FFFFF80"; | ||
constant ADDR_ORBIT_INTLK_STS : std_logic_vector(31 downto 0) := x"00000004"; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_X_OFFSET : integer := 0; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_X : std_logic_vector(31 downto 0) := x"00000001"; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_Y_OFFSET : integer := 1; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_Y : std_logic_vector(31 downto 0) := x"00000002"; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_LTC_X_OFFSET : integer := 2; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_LTC_X : std_logic_vector(31 downto 0) := x"00000004"; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_LTC_Y_OFFSET : integer := 3; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_LTC_Y : std_logic_vector(31 downto 0) := x"00000008"; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_ANY_OFFSET : integer := 4; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_ANY : std_logic_vector(31 downto 0) := x"00000010"; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_OFFSET : integer := 5; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER : std_logic_vector(31 downto 0) := x"00000020"; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_LTC_OFFSET : integer := 6; | ||
constant ORBIT_INTLK_STS_TRANS_BIGGER_LTC : std_logic_vector(31 downto 0) := x"00000040"; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_X_OFFSET : integer := 7; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_X : std_logic_vector(31 downto 0) := x"00000080"; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_Y_OFFSET : integer := 8; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_Y : std_logic_vector(31 downto 0) := x"00000100"; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_LTC_X_OFFSET : integer := 9; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_LTC_X : std_logic_vector(31 downto 0) := x"00000200"; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_LTC_Y_OFFSET : integer := 10; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_LTC_Y : std_logic_vector(31 downto 0) := x"00000400"; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_ANY_OFFSET : integer := 11; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_ANY : std_logic_vector(31 downto 0) := x"00000800"; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_OFFSET : integer := 12; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER : std_logic_vector(31 downto 0) := x"00001000"; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_LTC_OFFSET : integer := 13; | ||
constant ORBIT_INTLK_STS_ANG_BIGGER_LTC : std_logic_vector(31 downto 0) := x"00002000"; | ||
constant ORBIT_INTLK_STS_INTLK_OFFSET : integer := 14; | ||
constant ORBIT_INTLK_STS_INTLK : std_logic_vector(31 downto 0) := x"00004000"; | ||
constant ORBIT_INTLK_STS_INTLK_LTC_OFFSET : integer := 15; | ||
constant ORBIT_INTLK_STS_INTLK_LTC : std_logic_vector(31 downto 0) := x"00008000"; | ||
constant ADDR_ORBIT_INTLK_MIN_SUM : std_logic_vector(31 downto 0) := x"00000008"; | ||
constant ADDR_ORBIT_INTLK_TRANS_MAX_X : std_logic_vector(31 downto 0) := x"0000000C"; | ||
constant ADDR_ORBIT_INTLK_TRANS_MAX_Y : std_logic_vector(31 downto 0) := x"00000010"; | ||
constant ADDR_ORBIT_INTLK_ANG_MAX_X : std_logic_vector(31 downto 0) := x"00000014"; | ||
constant ADDR_ORBIT_INTLK_ANG_MAX_Y : std_logic_vector(31 downto 0) := x"00000018"; | ||
constant ADDR_ORBIT_INTLK_TRANS_MIN_X : std_logic_vector(31 downto 0) := x"0000001C"; | ||
constant ADDR_ORBIT_INTLK_TRANS_MIN_Y : std_logic_vector(31 downto 0) := x"00000020"; | ||
constant ADDR_ORBIT_INTLK_ANG_MIN_X : std_logic_vector(31 downto 0) := x"00000024"; | ||
constant ADDR_ORBIT_INTLK_ANG_MIN_Y : std_logic_vector(31 downto 0) := x"00000028"; | ||
constant ADDR_ORBIT_INTLK_TRANS_X_DIFF : std_logic_vector(31 downto 0) := x"0000002C"; | ||
constant ADDR_ORBIT_INTLK_TRANS_Y_DIFF : std_logic_vector(31 downto 0) := x"00000030"; | ||
constant ADDR_ORBIT_INTLK_ANG_X_DIFF : std_logic_vector(31 downto 0) := x"00000034"; | ||
constant ADDR_ORBIT_INTLK_ANG_Y_DIFF : std_logic_vector(31 downto 0) := x"00000038"; | ||
end package wb_orbit_intlk_regs_const_pkg; |
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---------------------------------------------------------------------------------- | ||
-- Copied from: -- | ||
-- https://ohwr.org/project/general-cores/blob/master/sim/vhdl/sim_wishbone.vhd -- | ||
---------------------------------------------------------------------------------- | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
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use work.wishbone_pkg.all; | ||
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package sim_wishbone is | ||
procedure init (signal wb_o: out t_wishbone_master_out); | ||
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-- Classic | ||
procedure write32 (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : std_logic_vector (31 downto 0); | ||
data : std_logic_vector (31 downto 0)); | ||
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procedure read32 (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : std_logic_vector (31 downto 0); | ||
data : out std_logic_vector (31 downto 0)); | ||
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-- PL: pipelined versions. | ||
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procedure write32_pl (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : std_logic_vector (31 downto 0); | ||
data : std_logic_vector (31 downto 0)); | ||
procedure read32_pl (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : std_logic_vector (31 downto 0); | ||
data : out std_logic_vector (31 downto 0)); | ||
procedure write32_pl (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : natural; | ||
data : std_logic_vector (31 downto 0)); | ||
procedure read32_pl (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : natural; | ||
data : out std_logic_vector (31 downto 0)); | ||
end sim_wishbone; | ||
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package body sim_wishbone is | ||
-- Generate a strobe pulse. | ||
procedure start_pl (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in) is | ||
begin | ||
wb_o.stb <= '1'; | ||
loop | ||
wait until rising_edge(clk); | ||
exit when wb_i.stall = '0'; | ||
end loop; | ||
wb_o.stb <= '0'; | ||
end start_pl; | ||
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procedure wait_ack (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in) is | ||
begin | ||
loop | ||
exit when wb_i.ack = '1'; | ||
wait until rising_edge(clk); | ||
end loop; | ||
wb_o.cyc <= '0'; | ||
wb_o.stb <= '0'; | ||
-- wb_o.adr <= (others => 'X'); | ||
-- this causes problems with cheby generated RAM interfaces | ||
wb_o.dat <= (others => 'X'); | ||
end wait_ack; | ||
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procedure init (signal wb_o: out t_wishbone_master_out) is | ||
begin | ||
wb_o.stb <= '0'; | ||
wb_o.cyc <= '0'; | ||
wb_o.adr <= (others => '0'); | ||
end init; | ||
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procedure write32 (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : std_logic_vector (31 downto 0); | ||
data : std_logic_vector (31 downto 0)) is | ||
begin | ||
wb_o.adr <= addr; | ||
wb_o.dat <= data; | ||
wb_o.sel <= "1111"; | ||
wb_o.we <= '1'; | ||
wb_o.cyc <= '1'; | ||
wb_o.stb <= '1'; | ||
wait until rising_edge(clk); | ||
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wait_ack (clk, wb_o, wb_i); | ||
wait until rising_edge(clk); | ||
end write32; | ||
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procedure read32 (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : std_logic_vector (31 downto 0); | ||
data : out std_logic_vector (31 downto 0)) is | ||
begin | ||
wb_o.adr <= addr; | ||
wb_o.we <= '0'; | ||
wb_o.cyc <= '1'; | ||
wb_o.stb <= '1'; | ||
wait until rising_edge(clk); | ||
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wait_ack (clk, wb_o, wb_i); | ||
data := wb_i.dat; | ||
wait until rising_edge(clk); | ||
end read32; | ||
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procedure write32_pl (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : std_logic_vector (31 downto 0); | ||
data : std_logic_vector (31 downto 0)) is | ||
begin | ||
wb_o.adr <= addr; | ||
wb_o.dat <= data; | ||
wb_o.sel <= "1111"; | ||
wb_o.we <= '1'; | ||
wb_o.cyc <= '1'; | ||
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start_pl (clk, wb_o, wb_i); | ||
wait_ack (clk, wb_o, wb_i); | ||
end write32_pl; | ||
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procedure read32_pl (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : std_logic_vector (31 downto 0); | ||
data : out std_logic_vector (31 downto 0)) is | ||
begin | ||
wb_o.adr <= addr; | ||
wb_o.we <= '0'; | ||
wb_o.cyc <= '1'; | ||
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start_pl (clk, wb_o, wb_i); | ||
wait_ack (clk, wb_o, wb_i); | ||
data := wb_i.dat; | ||
end read32_pl; | ||
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procedure write32_pl (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : natural; | ||
data : std_logic_vector (31 downto 0)) is | ||
begin | ||
write32_pl (clk, wb_o, wb_i, std_logic_vector (to_unsigned(addr, 32)), data); | ||
end write32_pl; | ||
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procedure read32_pl (signal clk : std_logic; | ||
signal wb_o: out t_wishbone_master_out; | ||
signal wb_i: in t_wishbone_master_in; | ||
addr : natural; | ||
data : out std_logic_vector (31 downto 0)) is | ||
begin | ||
read32_pl (clk, wb_o, wb_i, std_logic_vector (to_unsigned(addr, 32)), data); | ||
end read32_pl; | ||
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end sim_wishbone; |
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modules = { | ||
"local" : [ | ||
"../../modules", | ||
"../../ip_cores/general-cores", | ||
"../../ip_cores/infra-cores", | ||
"../../ip_cores/dsp-cores", | ||
] | ||
} | ||
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files = [ | ||
"xwb_orbit_intlk_tb.vhd", | ||
"../../sim/sim_wishbone.vhd", | ||
"../../sim/regs/wb_orbit_intlk_regs_const_pkg.vhd", | ||
] |
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*.o | ||
*.cf | ||
*.ghw | ||
xwb_orbit_intlk_tb |
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action = "simulation" | ||
sim_tool = "ghdl" | ||
top_module = "xwb_orbit_intlk_tb" | ||
target = "xilinx" | ||
syn_device = "xc7a200t" | ||
machine_pkg = "sirius_sr_250M" | ||
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modules = {"local" : ["../"]} | ||
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ghdl_opt = "--std=08 -frelaxed -fsynopsys" | ||
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sim_post_cmd = "ghdl -r --std=08 %s --wave=%s.ghw"%(top_module, top_module) |
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work/ | ||
*.fst |
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action = "simulation" | ||
sim_tool = "nvc" | ||
top_module = "xwb_orbit_intlk_tb" | ||
target = "xilinx" | ||
syn_device = "xc7a200t" | ||
machine_pkg = "sirius_sr_250M" | ||
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modules = {"local" : ["../"]} | ||
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nvc_opt = "--std=2008" | ||
nvc_elab_opt = "--no-collapse" | ||
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sim_post_cmd = "nvc -r --dump-arrays --exit-severity=error %s --wave=%s.fst --format=fst"%(top_module, top_module) |
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