Move wb_orbit_intlk ModelSim testbench to separated directory

This is in anticipation to creating a new testbench compatible with NVC and GHDL.
lnls-dig · Sep 20, 2024 · b3318e3 · b3318e3
1 parent 272e58b
commit b3318e3
Show file tree

Hide file tree

Showing 8 changed files with 33 additions and 33 deletions.
diff --git a/hdl/testbench/orbit_intlk/Manifest.py b/hdl/testbench/orbit_intlk/Manifest.py
diff --git a/hdl/testbench/orbit_intlk/modelsim/Manifest.py b/hdl/testbench/orbit_intlk/modelsim/Manifest.py
@@ -0,0 +1,32 @@
+action = "simulation"
+target = "xilinx"
+syn_device = "xc7a200t"
+sim_tool = "modelsim"
+top_module = "wb_orbit_intlk_tb"
+sim_top = "wb_orbit_intlk_tb"
+
+modules = {
+    "local" : [
+               "../../../modules/wb_orbit_intlk/",
+               "../../../ip_cores/general-cores",
+               "../../../ip_cores/infra-cores",
+               "../../../ip_cores/dsp-cores",
+    ]
+}
+
+files = [
+    "wb_orbit_intlk_tb.v",
+    "clk_rst.v",
+]
+
+include_dirs = [
+    ".",
+    "../../../sim",
+    "../../../sim/regs"
+    "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src",
+    "../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic",
+    "../../../ip_cores/general-cores/modules/wishbone/wb_spi_bidir",
+    "../../../ip_cores/general-cores/modules/wishbone/wb_spi"
+]
+
+vlog_opt = "+incdir+../../../sim/regs +incdir+../../../sim  +incdir+."
diff --git a/hdl/testbench/orbit_intlk/clk_rst.v → hdl/testbench/orbit_intlk/modelsim/clk_rst.v b/hdl/testbench/orbit_intlk/clk_rst.v → hdl/testbench/orbit_intlk/modelsim/clk_rst.v
diff --git a/hdl/testbench/orbit_intlk/defines.v → hdl/testbench/orbit_intlk/modelsim/defines.v b/hdl/testbench/orbit_intlk/defines.v → hdl/testbench/orbit_intlk/modelsim/defines.v
diff --git a/hdl/testbench/orbit_intlk/run.do → hdl/testbench/orbit_intlk/modelsim/run.do b/hdl/testbench/orbit_intlk/run.do → hdl/testbench/orbit_intlk/modelsim/run.do
@@ -1,4 +1,4 @@
-vlog wb_orbit_intlk_tb.v +incdir+"." +incdir+../../sim +incdir+../../sim/regs
+vlog wb_orbit_intlk_tb.v +incdir+"." +incdir+../../../sim +incdir+../../../sim/regs
 -- make -f Makefile
 -- output log file to file "output.log", set siulation resolution to "fs"
 vsim -l output.log \

diff --git a/hdl/testbench/orbit_intlk/timescale.v → ...estbench/orbit_intlk/modelsim/timescale.v b/hdl/testbench/orbit_intlk/timescale.v → ...estbench/orbit_intlk/modelsim/timescale.v
diff --git a/hdl/testbench/orbit_intlk/wave.do → hdl/testbench/orbit_intlk/modelsim/wave.do b/hdl/testbench/orbit_intlk/wave.do → hdl/testbench/orbit_intlk/modelsim/wave.do
diff --git a/...testbench/orbit_intlk/wb_orbit_intlk_tb.v → .../orbit_intlk/modelsim/wb_orbit_intlk_tb.v b/...testbench/orbit_intlk/wb_orbit_intlk_tb.v → .../orbit_intlk/modelsim/wb_orbit_intlk_tb.v