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Harmonize all Vivado synthesis and implementation flags
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Now all targets have the same synthesis and implementation flags. Also
changes the optimization strategy to "ExploreWithRemap" to improve
timing closure.
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augustofg committed Sep 5, 2024
1 parent d542910 commit 70859a2
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Showing 6 changed files with 32 additions and 7 deletions.
8 changes: 6 additions & 2 deletions hdl/syn/afc_v3/dbe_bpm2_bo_sirius/Manifest.py
Original file line number Diff line number Diff line change
Expand Up @@ -19,17 +19,21 @@
["steps.synth_design.args.retiming", "1"],
["steps.synth_design.args.assert", "1"],
["steps.opt_design.args.verbose", "1"],
["steps.opt_design.args.directive", "ExploreWithRemap"],
["steps.opt_design.is_enabled", "1"],
["steps.phys_opt_design.args.directive", "AlternateFlowWithRetiming"],
["steps.phys_opt_design.args.directive", "Explore"],
["steps.phys_opt_design.args.more options", "-verbose"],
["steps.phys_opt_design.is_enabled", "1"],
["steps.post_route_phys_opt_design.args.directive", "AddRetime"],
["steps.route_design.args.directive", "NoTimingRelaxation"],
["steps.route_design.args.more options", "-tns_cleanup"],
["steps.post_route_phys_opt_design.args.directive", "Explore"],
["steps.post_route_phys_opt_design.args.more options", "-verbose"],
["steps.post_route_phys_opt_design.is_enabled", "1"],
["steps.write_bitstream.args.verbose", "1"],
["steps.write_bitstream.args.bin_file", "true", "get_runs impl_1"]
]


board = "afc"

# For appending the afc_ref_design.xdc to synthesis
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5 changes: 4 additions & 1 deletion hdl/syn/afc_v3/dbe_bpm2_bo_sirius_with_dcc/Manifest.py
Original file line number Diff line number Diff line change
Expand Up @@ -19,15 +19,18 @@
["steps.synth_design.args.retiming", "1"],
["steps.synth_design.args.assert", "1"],
["steps.opt_design.args.verbose", "1"],
["steps.opt_design.args.directive", "ExploreWithRemap"],
["steps.opt_design.is_enabled", "1"],
["steps.phys_opt_design.args.directive", "Explore"],
["steps.phys_opt_design.args.more options", "-verbose"],
["steps.phys_opt_design.is_enabled", "1"],
["steps.route_design.args.directive", "NoTimingRelaxation"],
["steps.route_design.args.more options", "-tns_cleanup"],
["steps.post_route_phys_opt_design.args.directive", "Explore"],
["steps.post_route_phys_opt_design.args.more options", "-verbose"],
["steps.post_route_phys_opt_design.is_enabled", "1"],
["steps.write_bitstream.args.verbose", "1"],
["steps.write_bitstream.args.bin_file", "true", "get_runs impl_1"],
["steps.write_bitstream.args.bin_file", "true", "get_runs impl_1"]
]

board = "afc"
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7 changes: 5 additions & 2 deletions hdl/syn/afc_v3/dbe_bpm2_sr_sirius/Manifest.py
Original file line number Diff line number Diff line change
Expand Up @@ -19,11 +19,14 @@
["steps.synth_design.args.retiming", "1"],
["steps.synth_design.args.assert", "1"],
["steps.opt_design.args.verbose", "1"],
["steps.opt_design.args.directive", "ExploreWithRemap"],
["steps.opt_design.is_enabled", "1"],
["steps.phys_opt_design.args.directive", "AlternateFlowWithRetiming"],
["steps.phys_opt_design.args.directive", "Explore"],
["steps.phys_opt_design.args.more options", "-verbose"],
["steps.phys_opt_design.is_enabled", "1"],
["steps.post_route_phys_opt_design.args.directive", "AddRetime"],
["steps.route_design.args.directive", "NoTimingRelaxation"],
["steps.route_design.args.more options", "-tns_cleanup"],
["steps.post_route_phys_opt_design.args.directive", "Explore"],
["steps.post_route_phys_opt_design.args.more options", "-verbose"],
["steps.post_route_phys_opt_design.is_enabled", "1"],
["steps.write_bitstream.args.verbose", "1"],
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3 changes: 3 additions & 0 deletions hdl/syn/afc_v3/dbe_bpm2_sr_sirius_with_dcc/Manifest.py
Original file line number Diff line number Diff line change
Expand Up @@ -19,10 +19,13 @@
["steps.synth_design.args.retiming", "1"],
["steps.synth_design.args.assert", "1"],
["steps.opt_design.args.verbose", "1"],
["steps.opt_design.args.directive", "ExploreWithRemap"],
["steps.opt_design.is_enabled", "1"],
["steps.phys_opt_design.args.directive", "Explore"],
["steps.phys_opt_design.args.more options", "-verbose"],
["steps.phys_opt_design.is_enabled", "1"],
["steps.route_design.args.directive", "NoTimingRelaxation"],
["steps.route_design.args.more options", "-tns_cleanup"],
["steps.post_route_phys_opt_design.args.directive", "Explore"],
["steps.post_route_phys_opt_design.args.more options", "-verbose"],
["steps.post_route_phys_opt_design.is_enabled", "1"],
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7 changes: 5 additions & 2 deletions hdl/syn/afc_v3/dbe_pbpm/Manifest.py
Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,14 @@
["steps.synth_design.args.retiming", "1"],
["steps.synth_design.args.assert", "1"],
["steps.opt_design.args.verbose", "1"],
["steps.opt_design.args.directive", "ExploreWithRemap"],
["steps.opt_design.is_enabled", "1"],
["steps.phys_opt_design.args.directive", "AlternateFlowWithRetiming"],
["steps.phys_opt_design.args.directive", "Explore"],
["steps.phys_opt_design.args.more options", "-verbose"],
["steps.phys_opt_design.is_enabled", "1"],
["steps.post_route_phys_opt_design.args.directive", "AddRetime"],
["steps.route_design.args.directive", "NoTimingRelaxation"],
["steps.route_design.args.more options", "-tns_cleanup"],
["steps.post_route_phys_opt_design.args.directive", "Explore"],
["steps.post_route_phys_opt_design.args.more options", "-verbose"],
["steps.post_route_phys_opt_design.is_enabled", "1"],
["steps.write_bitstream.args.verbose", "1"],
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9 changes: 9 additions & 0 deletions hdl/syn/afc_v3/dbe_pbpm_with_dcc/Manifest.py
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,16 @@
["steps.synth_design.args.retiming", "1"],
["steps.synth_design.args.assert", "1"],
["steps.opt_design.args.verbose", "1"],
["steps.opt_design.args.directive", "ExploreWithRemap"],
["steps.opt_design.is_enabled", "1"],
["steps.phys_opt_design.args.directive", "Explore"],
["steps.phys_opt_design.args.more options", "-verbose"],
["steps.phys_opt_design.is_enabled", "1"],
["steps.route_design.args.directive", "NoTimingRelaxation"],
["steps.route_design.args.more options", "-tns_cleanup"],
["steps.post_route_phys_opt_design.args.directive", "Explore"],
["steps.post_route_phys_opt_design.args.more options", "-verbose"],
["steps.post_route_phys_opt_design.is_enabled", "1"],
["steps.write_bitstream.args.verbose", "1"],
["steps.write_bitstream.args.bin_file", "true", "get_runs impl_1"]
]
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